公开(公告)号：US20230028400A1

公开(公告)日：2023-01-26

申请号：US17958301

申请日：2022-09-30

Applicant: Samsung Display Co., Ltd.

Inventor： Sewan SON ,  Moo Soon KO ,  Ji Ryun PARK ,  Jin Sung AN ,  Min Woo WOO ,  Seong Jun LEE ,  Wang Woo LEE ,  Jeong-Soo LEE ,  Ji Seon LEE ,  Deuk Myung JI

IPC: H01L27/32

Abstract: A display device comprises a substrate including display and peripheral areas, a semiconductor element, a pixel structure, and a plurality of dummy patterns. The semiconductor element is disposed in the display area on the substrate, and the pixel structure is disposed on the semiconductor element. The dummy patterns which have stacked structure are disposed in the peripheral area on the substrate, and contain a material identical to a material constituting the semiconductor element. The dummy patterns are arranged in a grid shape in different layers, and each of the dummy patterns includes a central portion and an edge portion surrounding the central portion. The edge portions of dummy patterns which are adjacent to each other in the different layers among the dummy patterns are overlapped each other in a direction from the substrate to the pixel structure.

公开(公告)号：US20220180820A1

公开(公告)日：2022-06-09

申请号：US17680964

申请日：2022-02-25

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Seon LEE ,  Jin Sung AN ,  Seok Je SEONG ,  Seong Jun LEE ,  Se Wan SON

IPC: G09G3/3291

Abstract: A display device includes a substrate, a first active pattern, a first gate electrode, a second active pattern, a second gate electrode, a first connecting pattern, and a second connecting pattern. The first connecting pattern is disposed on the second active pattern and is electrically connected to the first gate electrode, and the second connecting pattern is disposed on the first connecting pattern and is electrically connected to the first connecting pattern and the second active pattern.

公开(公告)号：US20210280609A1

公开(公告)日：2021-09-09

申请号：US17144273

申请日：2021-01-08

Applicant: Samsung Display Co., Ltd.

Inventor： Jin Sung AN ,  Seok Je SEONG ,  Seong Jun LEE ,  Ji Seon LEE

IPC: H01L27/12

Abstract: A display device includes a first active pattern, a first conductive pattern including a gate electrode overlapping the first active pattern, a first gate line overlapping the first active pattern and extending in a first direction, and a second gate line extending in the first direction, a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction, a second active pattern disposed on the second conductive pattern and including a material different from a material of the first active pattern, and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping the third gate line and connected to the third gate line, and a second upper electrode overlapping the fourth gate line and connected to the fourth gate line.

公开(公告)号：US20210280140A1

公开(公告)日：2021-09-09

申请号：US17193281

申请日：2021-03-05

Applicant: Samsung Display Co., Ltd.

Inventor： Ji Seon LEE ,  Jin Sung AN ,  Seok Je SEONG ,  Seong Jun LEE ,  Se Wan SON

IPC: G09G3/3291

Abstract: A display device includes a substrate, a first active pattern, a first gate electrode, a second active pattern, a second gate electrode, a first connecting pattern, and a second connecting pattern. The first connecting pattern is disposed on the second active pattern and is electrically connected to the first gate electrode, and the second connecting pattern is disposed on the first connecting pattern and is electrically connected to the first connecting pattern and the second active pattern.

公开(公告)号：US20200381504A1

公开(公告)日：2020-12-03

申请号：US16799296

申请日：2020-02-24

Applicant: Samsung Display Co., LTD.

Inventor： Jin Sung AN ,  Young Woo PARK ,  Se Wan SON ,  Moo Soon KO ,  Jeong-Soo LEE ,  Ji Seon LEE ,  Deuk Myung JI

IPC: H01L27/32 ,  H01L51/56 ,  G09G3/3266 ,  G09G3/3275 ,  H01L51/52

Abstract: A display device including: a substrate; an active layer, and including channel and conductive regions and; a first conductive layer including a driving gate electrode and a scan line in a first direction; a second conductive layer including a storage line; a third conductive layer including a first connecting member above the storage line; an insulating layer between the storage line and the first connecting member; and a data line and a driving voltage line crossing the scan line in a second direction, wherein the first connecting member electrically connects the driving gate electrode and a conductive region, the driving voltage line overlaps the first connecting member, the insulating layer includes first and second sub-insulating layers, and an edge of the second sub-insulating layer substantially overlaps an edge of the first connecting member in a thickness direction of the display device.

公开(公告)号：US20180350889A1

公开(公告)日：2018-12-06

申请号：US15944832

申请日：2018-04-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SE WAN SON ,  Jung Hwa KIM ,  Jin Sung AN ,  Wang Woo LEE ,  Ji Seon LEE ,  Moo Soon KO

IPC: H01L27/32

Abstract: A pattern structure for a display device includes a substrate, a protrusion pattern on the substrate, a first conductive pattern covering an upper surface of the protrusion pattern, an interlayer insulating layer on the first conductive pattern and including a contact hole, and a second conductive pattern on the interlayer insulating layer and connected to the first conductive pattern. The contact hole overlaps the protrusion pattern and the first conductive pattern.

公开(公告)号：US20250107374A1

公开(公告)日：2025-03-27

申请号：US18975487

申请日：2024-12-10

Applicant: Samsung Display Co., Ltd.

Inventor： Seung Hwan CHO ,  Beom Yeol PARK ,  Hyeon Woo SHIN ,  Ji Seon LEE ,  Won Suk CHOI ,  Yoon Sun CHOI

IPC: H10K59/131 ,  H10K59/126

Abstract: A display device includes a driving transistor; a transistor connected to the driving transistor; a first insulating layer; a first data conductive layer including a first connection pattern; a second insulating layer including a lower via hole; a second data conductive layer including a second connection pattern connected to the first connection pattern and a first conductive line; a third insulating layer including an intermediate via hole; a third data conductive layer including a third connection pattern connected to the second connection pattern, a second conductive line extending in a second direction, and a first data line which extends in the second direction; a fourth insulating layer including an upper via hole; and a light emitting element disposed including a first electrode, wherein at least two of the lower via hole, the intermediate via hole, and the upper via hole overlap each other in a third direction.

公开(公告)号：US20240372045A1

公开(公告)日：2024-11-07

申请号：US18421690

申请日：2024-01-24

Applicant: Samsung Display Co., LTD.

Inventor： Kyeong Woo JANG ,  Se Wan SON ,  Sung Ho KIM ,  Min Woo WOO ,  Seung Hyun LEE ,  Wang Woo LEE ,  Ji Seon LEE ,  Sug Woo JUNG ,  Hye Ri CHO

IPC: H01L33/54 ,  H01L25/075

Abstract: A display device includes a substrate including a display area surrounded by a non-display area, a bank structure disposed on the substrate in the display area and including a plurality of openings, a plurality of light emitting elements disposed in the openings, a first dam disposed on the substrate in the non-display area and spaced apart from the bank structure, and a second dam spaced apart from the first dam in the non-display area, wherein the bank structure includes a first bank layer and a second bank layer disposed on the first bank layer, wherein the first dam includes a first sub-dam structure and a second sub-dam structure disposed on the first sub-dam structure, and the second bank layer includes tips protruding from sidewalls of the first bank layer, and the second sub-dam structure includes tips protruding from sidewalls of the first sub-dam structure.

公开(公告)号：US20240107840A1

公开(公告)日：2024-03-28

申请号：US18526207

申请日：2023-12-01

Applicant: Samsung Display Co., LTD.

Inventor： Se Wan SON ,  Moo Soon KO ,  Kyung Hyun BAEK ,  Seok Je SEONG ,  Jae Hyun LEE ,  Jeong-Soo LEE ,  Ji Seon LEE ,  Yoon-Jong CHO

IPC: H10K59/131 ,  H10K59/124 ,  H10K59/126

CPC classification number: H10K59/131 ,  H10K59/124 ,  H10K59/126 ,  G09G3/32 ,  G09G2300/0809

Abstract: A display device includes a first semiconductor layer disposed on a substrate; a first insulating layer disposed on the first semiconductor layer; a scan line disposed on the first insulating layer; a second insulating layer on the scan line; an inverted scan line on the second insulating layer; a third insulating layer disposed on the inverted scan line; a second semiconductor layer disposed on the third insulating layer; a fourth insulating layer disposed on the second semiconductor layer; an initializing voltage line disposed on the fourth insulating layer and overlapping the scan line; a first transistor including a channel disposed in the first semiconductor layer and receiving a gate signal through the scan line; and a second transistor including a channel disposed in the second semiconductor layer and receiving a gate signal through the inverted scan line.

公开(公告)号：US20230419886A1

公开(公告)日：2023-12-28

申请号：US18458526

申请日：2023-08-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jin Sung AN ,  Seok Je SEONG ,  Ji Seon LEE ,  Se Wan SON

IPC: G09G3/32 ,  H01L33/62 ,  H01L33/16

CPC classification number: G09G3/32 ,  H01L33/62 ,  H01L33/16 ,  G09G2310/0267 ,  G09G2300/0426 ,  G09G2310/0275

Abstract: A display device includes a substrate, a polycrystalline semiconductor layer including a channel of a driving transistor, and a channel of a seventh transistor, a gate electrode of the driving transistor overlapping the channel thereof, a gate electrode of the seventh transistor overlapping the channel thereof, an oxide semiconductor layer including a channel of a fourth transistor, a gate electrode thereof overlapping the channel of the fourth transistor, a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and the gate electrode of the fourth transistor being position on a same layer, and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being positioned on different layers from each other.