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公开(公告)号：US20240363803A1
公开(公告)日：2024-10-31
申请号：US18766027
申请日：2024-07-08
Applicant: Samsung Display Co., Ltd.
Inventor： Dae Hyun KIM , Jong Hyuk KANG , Joo Yeol LEE , Hyun Deok IM , Chi O CHO , Hyun Min CHO
IPC: H01L33/24 , G09G3/32 , H01L25/075 , H01L27/12 , H01L27/15 , H01L33/00 , H01L33/16 , H01L33/32 , H01L33/38 , H01L33/44
CPC classification number: H01L33/24 , H01L27/156 , H01L33/007 , H01L33/0075 , H01L33/16 , H01L33/325 , H01L33/38 , H01L33/44 , G09G3/32 , G09G2300/0452 , G09G2310/0278 , H01L25/0753 , H01L27/1214 , H01L2224/95085 , H01L2933/0016 , H01L2933/0025
Abstract: A light emitting device including first and second electrodes spaced apart from each other on a substrate, at least one bar-type LED having a first end on the first electrode and a second end on the second electrode, and an insulative support body between the substrate and the bar-type LED. The at least one bar-type LED has a length greater than a width.
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公开(公告)号：US12125946B2
公开(公告)日：2024-10-22
申请号：US17664577
申请日：2022-05-23
Applicant: Silanna UV Technologies Pte Ltd
Inventor： Petar Atanackovic
IPC: H01L33/26 , H01L21/02 , H01L23/66 , H01L27/15 , H01L29/15 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/51 , H01L29/66 , H01L29/778 , H01L29/786 , H01L33/00 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34
CPC classification number: H01L33/26 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/02458 , H01L21/02507 , H01L23/66 , H01L27/15 , H01L29/151 , H01L29/2003 , H01L29/24 , H01L29/267 , H01L29/517 , H01L29/66462 , H01L29/7869 , H01L33/002 , H01L33/007 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34 , H01L29/778 , H01L29/7786 , H01L2223/6627
Abstract: The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.
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公开(公告)号：US12095006B2
公开(公告)日：2024-09-17
申请号：US17664569
申请日：2022-05-23
Applicant: Silanna UV Technologies Pte Ltd
Inventor： Petar Atanackovic
IPC: H01L33/26 , H01L21/02 , H01L23/66 , H01L27/15 , H01L29/15 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/51 , H01L29/66 , H01L29/778 , H01L29/786 , H01L33/00 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34
CPC classification number: H01L33/26 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/02458 , H01L21/02507 , H01L23/66 , H01L27/15 , H01L29/151 , H01L29/2003 , H01L29/24 , H01L29/267 , H01L29/517 , H01L29/66462 , H01L29/7869 , H01L33/002 , H01L33/007 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34 , H01L29/778 , H01L29/7786 , H01L2223/6627
Abstract: The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.
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公开(公告)号：US12080824B2
公开(公告)日：2024-09-03
申请号：US17645523
申请日：2021-12-22
Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
Inventor： Guy Feuillet , François Templier , Jesus Zuniga Perez , Philippe Vennegues
CPC classification number: H01L33/0075 , H01L33/0093 , H01L33/16 , H01L33/32 , H01L2933/0066
Abstract: A method for producing an optoelectronic device having nitride-based microLEDs includes providing an assembly having at least one growth substrate and a nitride structure, where the nitride structure has a semipolar nitride layer that includes an active stack and crystallites extending from facets of the growth substrate with a crystalline orientation {111} to the first face of the semipolar nitride layer and providing an integrated control circuit featuring electric connection pads. The assembly is placed on the integrated control circuit, the growth substrate and the crystallites are removed, and trenches are formed in the stack so as to delimit a plurality of islets, each islet being configured to form a microLED.
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公开(公告)号：US20240250217A1
公开(公告)日：2024-07-25
申请号：US18408137
申请日：2024-01-09
Applicant: Apple Inc.
Inventor： Xiaobin Xin , Dmitry S Sizov , Chi-Kang Li , Steve M Ting , Fang Ou , David P Bour
Abstract: Light emitting diodes with regrown semiconductor layers and methods of manufacture are described. In an embodiment, a light emitting diode includes a base structure including a first cladding layer and a pillar structure protruding from the base layer. The pillar structure includes a mesa structure and a second cladding layer that includes a plug portion that is laterally adjacent to a plurality of quantum well layers of the mesa structure.
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Patent Agency Ranking
公开(公告)号：US20240250214A1
公开(公告)日：2024-07-25
申请号：US18589784
申请日：2024-02-28
Applicant: Japan Display Inc.
Inventor： Hiroumi KINJO , Masumi NISHIMURA , Hayata AOKI
Abstract: A gallium nitride-based semiconductor device includes an amorphous substrate, a conductive alignment layer on the amorphous substrate, a gallium nitride-based semiconductor layer on the conductive alignment layer, and an auxiliary electrode layer in contact with the conductive alignment layer. The auxiliary electrode layer is arranged around a periphery portion of the conductive alignment layer.
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公开(公告)号：US20240170612A1
公开(公告)日：2024-05-23
申请号：US18423986
申请日：2024-01-26
Applicant: Silanna UV Technologies Pte Ltd
Inventor： Petar Atanackovic
IPC: H01L33/26 , H01L21/02 , H01L23/66 , H01L27/15 , H01L29/15 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/51 , H01L29/66 , H01L29/786 , H01L33/00 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34
CPC classification number: H01L33/26 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/02458 , H01L21/02507 , H01L23/66 , H01L27/15 , H01L29/151 , H01L29/2003 , H01L29/24 , H01L29/267 , H01L29/517 , H01L29/66462 , H01L29/7869 , H01L33/002 , H01L33/007 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34 , H01L29/7786 , H01L2223/6627
Abstract: In some embodiments, the techniques described herein relate to an epitaxial oxide transistor. The transistor can include: a substrate; a channel layer including a first epitaxial semiconductor layer on the substrate; a gate layer including a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; a source electrode and a drain electrode coupled to the channel layer; and a gate electrode coupled to the gate layer. The first epitaxial semiconductor layer can include a first polar oxide material and the second epitaxial semiconductor layer can include a second polar oxide material. The first polar oxide material and the second polar oxide material can include cation-polar surfaces oriented towards or away from the substrate, and the second polar oxide material can include a wider bandgap than the first polar oxide material.
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公开(公告)号：US11978825B2
公开(公告)日：2024-05-07
申请号：US17388949
申请日：2021-07-29
Applicant: Apple Inc.
Inventor： Kelly McGroddy , Hsin-Hua Hu , Andreas Bibl , Clayton Ka Tsun Chan , Daniel Arthur Haeger
IPC: H01L33/14 , H01L23/00 , H01L25/075 , H01L27/01 , H01L27/15 , H01L33/00 , H01L33/06 , H01L33/30 , H01L33/42 , G09G3/32 , H01L33/16 , H01L33/20
CPC classification number: H01L33/145 , H01L24/75 , H01L24/95 , H01L25/0753 , H01L27/016 , H01L27/156 , H01L33/0093 , H01L33/06 , H01L33/14 , H01L33/30 , H01L33/42 , G09G3/32 , H01L33/0016 , H01L33/0095 , H01L33/16 , H01L33/20 , H01L2224/75305 , H01L2224/75725 , H01L2224/7598 , H01L2224/82203 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/12041 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2924/12044 , H01L2924/00
Abstract: Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.
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公开(公告)号：US20240072205A1
公开(公告)日：2024-02-29
申请号：US18480323
申请日：2023-10-03
Applicant: Silanna UV Technologies Pte Ltd
Inventor： Petar Atanackovic
IPC: H01L33/26 , H01L21/02 , H01L23/66 , H01L27/15 , H01L29/15 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/51 , H01L29/66 , H01L29/786 , H01L33/00 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34
CPC classification number: H01L33/26 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/02458 , H01L21/02507 , H01L23/66 , H01L27/15 , H01L29/151 , H01L29/2003 , H01L29/24 , H01L29/267 , H01L29/517 , H01L29/66462 , H01L29/7869 , H01L33/002 , H01L33/007 , H01L33/06 , H01L33/16 , H01L33/18 , H01L33/62 , H01S5/34 , H01L29/7786 , H01L2223/6627
Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, the techniques described herein relate to a transistor, including: a substrate including a first oxide material; an epitaxial oxide layer on the substrate including a second oxide material with a first bandgap; a gate layer on the epitaxial oxide layer, the gate layer including a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The second oxide material can include: one or two of Li, Ni, Al, Ga, Mg, and Zn; Ge; and O. The second oxide can also include (NixMgyZn1-x-y)2GeO4 wherein 0≤x≤1 and 0≤y≤1. The electrical contacts can include: a source electrical contact coupled to the epitaxial oxide layer; a drain electrical contact coupled to the epitaxial oxide layer; and a first gate electrical contact coupled to the gate layer.
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公开(公告)号：US20240063340A1
公开(公告)日：2024-02-22
申请号：US17642057
申请日：2020-09-10
Applicant: The Regents of the University of California
Inventor： Stacia Keller , Umesh K. Mishra , Shubhra Pasayat , Chirag Gupta
IPC: H01L33/32 , H01L33/16 , H01L33/12 , H01L25/075 , H01L33/20
CPC classification number: H01L33/32 , H01L33/16 , H01L33/12 , H01L25/0753 , H01L33/20
Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.
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