公开(公告)号：US12191246B2

公开(公告)日：2025-01-07

申请号：US18505613

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： KwanJai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/498 ,  H01L23/00

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

公开(公告)号：US11764140B2

公开(公告)日：2023-09-19

申请号：US17391164

申请日：2021-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uk Han ,  Duck Gyu Kim ,  Min Ki Kim ,  Jae-Min Jung ,  Jeong-Kyu Ha

IPC: H01L23/58 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/585

Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

公开(公告)号：US11600608B2

公开(公告)日：2023-03-07

申请号：US17204225

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichul Kim ,  Chajea Jo ,  Sang-Uk Han ,  Kyoung Soon Cho ,  Jae Choon Kim ,  Woohyun Park

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/18

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US10985152B2

公开(公告)日：2021-04-20

申请号：US16503121

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichul Kim ,  Chajea Jo ,  Sang-Uk Han ,  Kyoung Soon Cho ,  Jae Choon Kim ,  Woohyun Park

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/18

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US09177904B2

公开(公告)日：2015-11-03

申请号：US13769520

申请日：2013-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Min Jung ,  Sang-Uk Han ,  KwanJai Lee ,  KyongSoon Cho ,  Jeong-Kyu Ha

IPC: G02F1/1343 ,  H01L23/498 ,  H01L51/52

CPC classification number: H01L25/167 ,  H01L23/49827 ,  H01L23/4985 ,  H01L27/323 ,  H01L27/3276 ,  H01L27/3288 ,  H01L51/52 ,  H01L51/524 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate.

Abstract translation: 可以提供包括其的片上胶片包装和装置组件。 该装置组件包括：薄膜封装，其包括半导体芯片，连接到薄膜封装的一端的面板基板，设置在面板基板上的显示面板，以及连接到薄膜封装的另一端的控制部件。 薄膜封装包括薄膜基板，设置在薄膜基板的顶表面上的第一布线和设置在薄膜基板的底表面上的第二布线。