公开(公告)号：US11923259B2

公开(公告)日：2024-03-05

申请号：US17985166

申请日：2022-11-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Tsung-Fu Tsai

IPC分类号： H01L23/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18 ,  H01L23/29

CPC分类号： H01L23/18 ,  H01L23/3185 ,  H01L23/3675 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L23/295 ,  H01L2224/73204

摘要： A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.

公开(公告)号：US20240063066A1

公开(公告)日：2024-02-22

申请号：US17891665

申请日：2022-08-19

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Tomita Yoshihiro ,  Adel A. Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi ,  Yi Shi ,  Batao Zhang ,  Wenhao Li ,  Feras Eid

IPC分类号： H01L23/04 ,  H01L25/065 ,  H01L23/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/46 ,  H01L23/367

CPC分类号： H01L23/041 ,  H01L25/0652 ,  H01L23/18 ,  H01L24/08 ,  H01L23/481 ,  H01L23/46 ,  H01L23/367 ,  H01L2224/08145 ,  H01L2224/05599 ,  H01L24/05 ,  H01L2224/80379 ,  H01L24/80 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/131 ,  H01L24/13 ,  H01L2224/29099 ,  H01L24/29

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

公开(公告)号：US20230011041A1

公开(公告)日：2023-01-12

申请号：US17857227

申请日：2022-07-05

申请人： SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

发明人： Soichiro UMEDA ,  Atsushi KYUTOKU

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/18

摘要： A semiconductor device includes: an insulating substrate; a first conductor portion and a second conductor portion that are formed on the insulating substrate; a semiconductor element disposed on the first conductor portion; a first terminal having a flat plate-shape that is connected to a first electrode of the semiconductor element; a second terminal having a flat plate-shape that is connected to the first conductor portion; and a sealing resin that seals the insulating substrate, the first conductor portion, the second conductor portion, and the semiconductor element. Each of the first terminal and the second terminal includes: an inner terminal portion disposed inside the sealing resin; and an outer terminal portion disposed in a state of being exposed to an exterior of the sealing resin, and a female thread portion is provided in the outer terminal portion of each of the first terminal and the second terminal.

公开(公告)号：US11444013B2

公开(公告)日：2022-09-13

申请号：US16707145

申请日：2019-12-09

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Bora Baloglu ,  Ron Huemoeller ,  Curtis Zwenger

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/18 ,  H01L23/31

摘要： An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.

公开(公告)号：US11424173B2

公开(公告)日：2022-08-23

申请号：US17068064

申请日：2020-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18 ,  H01L21/822 ,  H01L25/11

摘要： An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.

公开(公告)号：US11315883B2

公开(公告)日：2022-04-26

申请号：US16680978

申请日：2019-11-12

申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

发明人： Suming Hu ,  Roden Topacio ,  Farshad Ghahghahi ,  Jianguo Li ,  Andrew Kwan Wai Leung

IPC分类号： H01L23/544 ,  H01L23/18 ,  H01L23/12

摘要： An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.

公开(公告)号：US11133261B2

公开(公告)日：2021-09-28

申请号：US15845336

申请日：2017-12-18

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Chee Kheong Yoon ,  Jia Yan Go

IPC分类号： H01L23/538 ,  H01L25/10 ,  H05K1/18 ,  H01L25/00 ,  H01L25/18 ,  H01L23/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

摘要： An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.

公开(公告)号：US11127644B2

公开(公告)日：2021-09-21

申请号：US16570776

申请日：2019-09-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Yang Yu ,  Hai-Ming Chen ,  Yu-Min Liang ,  Jung Wei Cheng ,  Chien-Hsun Lee

IPC分类号： H01L23/18 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00

摘要： An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.

公开(公告)号：US20210066175A1

公开(公告)日：2021-03-04

申请号：US16844199

申请日：2020-04-09

申请人： Mitsubishi Electric Corporation

发明人： Satoshi KONDO ,  Hidetoshi ISHIBASHI ,  Hiroshi YOSHIDA ,  Nobuhiro ASAJI ,  Junji FUJINO ,  Yusuke ISHIYAMA ,  Hodaka ROKUBUICHI

IPC分类号： H01L23/498 ,  H01L23/28 ,  H01L23/18 ,  H05K3/10 ,  H05K3/34 ,  H05K3/30 ,  H01L23/00

摘要： A semiconductor module includes: an insulated circuit board; a semiconductor device mounted on the insulated circuit board; a printed wiring board arranged above the insulated circuit board and the semiconductor device and having a through-hole; a metal pile having a lower end bonded to an upper surface of the semiconductor device and a cylindrical portion penetrating through the through-hole and bonded to the printed wiring board; a case surrounding the insulated circuit board, the semiconductor device, the printed wiring board and the metal pile; and a sealing material sealing an inside of the case.

公开(公告)号：US10804178B2

公开(公告)日：2020-10-13

申请号：US16697898

申请日：2019-11-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18 ,  H01L21/822 ,  H01L25/11

摘要： An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.