公开(公告)号：US09721926B2

公开(公告)日：2017-08-01

申请号：US14825403

申请日：2015-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong-Hwan Choe ,  Tae-Joo Hwang ,  Tae-Hong Min ,  Young-Kun Jee ,  Sang-Uk Han

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one silicon-through-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

公开(公告)号：US09054228B2

公开(公告)日：2015-06-09

申请号：US14160008

申请日：2014-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung Choi ,  Jong-Youn Kim ,  Sang-Wook Park ,  Hae-Jung Yu ,  In-Young Lee ,  Sang-Uk Han ,  Ji-Seok Hong

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract translation: 提供了包括散热器的半导体封装及其形成方法。 半导体封装可以包括顺序堆叠的第一半导体芯片，第二半导体芯片和散热器。 半导体封装还可以包括围绕第二半导体芯片并直接接触第二半导体芯片的侧壁的热界面材料（TIM）层。 TIM层的上表面可以直接接触散热器的下表面，并且TIM层的侧壁可以与散热器的侧壁基本上共面。 在一些实施例中，第一半导体芯片的侧壁可以与TIM层的侧壁基本共面。

公开(公告)号：US11569201B2

公开(公告)日：2023-01-31

申请号：US17509750

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Ji Hwang Kim ,  Jisun Yang ,  Seunghoon Yeon ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

公开(公告)号：US11152416B2

公开(公告)日：2021-10-19

申请号：US16507623

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-Uk Han

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US09620389B2

公开(公告)日：2017-04-11

申请号：US14967490

申请日：2015-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Youngshin Kwon ,  KwanJai Lee ,  Jae-Min Jung ,  KyongSoon Cho ,  Sang-Uk Han

IPC: H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/10 ,  H01L23/00 ,  H01L23/495 ,  H05K3/00 ,  H01L21/56 ,  H01L21/78 ,  H05K1/18 ,  H05K3/42

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

公开(公告)号：US08853694B2

公开(公告)日：2014-10-07

申请号：US13669031

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Han ,  Jeong-Kyu Ha ,  Young-Shin Kwon ,  Seung-Hwan Kim ,  Kwan-Jai Lee

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/495 ,  H01L21/66 ,  H01L23/14

CPC classification number: H01L23/49524 ,  H01L22/32 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/29099 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract translation: 提供了一种薄膜（COF）封装和具有该芯片的半导体。 所述COF封装可以包括柔性膜，所述柔性膜具有与所述第一表面和所述第二表面相对并彼此相对并且包括从所述第一表面穿过所述第二表面的导电通孔，所述第一和第二导电图案分别位于所述第一表面和所述第二表面上， 集成电路（IC）芯片在第一表面上并与第一导电图案电连接，测试焊盘与导电通孔重叠并且电连接到第一导电 图案和第二导电图案，并且外部连接图案在与导电通孔间隔开的第二表面上并电连接到第二导电图案。

公开(公告)号：US20130175528A1

公开(公告)日：2013-07-11

申请号：US13669031

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Han ,  Jeong-Kyu Ha ,  Young-Shin Kwon ,  Seung-Hwan Kim ,  Kwan-Jai Lee

IPC: H01L23/485

CPC classification number: H01L23/49524 ,  H01L22/32 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/29099 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract translation: 提供了一种薄膜（COF）封装和具有该芯片的半导体。 所述COF封装可以包括柔性膜，所述柔性膜具有与所述第一表面和所述第二表面相对并彼此相对并且包括从所述第一表面穿过所述第二表面的导电通孔，所述第一和第二导电图案分别位于所述第一表面和所述第二表面上， 集成电路（IC）芯片在第一表面上并与第一导电图案电连接，测试焊盘与导电通孔重叠并且电连接到第一导电 图案和第二导电图案，并且外部连接图案在与导电通孔间隔开的第二表面上并电连接到第二导电图案。

公开(公告)号：US10750112B2

公开(公告)日：2020-08-18

申请号：US16129010

申请日：2018-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hwang Kim ,  Hyo-Eun Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Sang-Uk Han

IPC: H04N5/369 ,  H04N5/225 ,  G02B5/20 ,  H01L27/146

Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.

公开(公告)号：US10510737B2

公开(公告)日：2019-12-17

申请号：US15786698

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichul Kim ,  Chajea Jo ,  Sang-Uk Han ,  Kyoung Soon Cho ,  Jae Choon Kim ,  Woohyun Park

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L23/18

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US10199319B2

公开(公告)日：2019-02-05

申请号：US15485794

申请日：2017-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Bo Shim ,  Sang-Uk Han ,  Yun-Seok Choi ,  Ji-Hwang Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.