Semiconductor package including a redistribution line

    公开(公告)号:US11152416B2

    公开(公告)日:2021-10-19

    申请号:US16507623

    申请日:2019-07-10

    Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

    CHIP ON FILM PACKAGE INCLUDING TEST PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME
    7.
    发明申请
    CHIP ON FILM PACKAGE INCLUDING TEST PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME 有权
    芯片封装包括测试垫和包括其中的半导体器件

    公开(公告)号:US20130175528A1

    公开(公告)日:2013-07-11

    申请号:US13669031

    申请日:2012-11-05

    Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

    Abstract translation: 提供了一种薄膜(COF)封装和具有该芯片的半导体。 所述COF封装可以包括柔性膜,所述柔性膜具有与所述第一表面和所述第二表面相对并彼此相对并且包括从所述第一表面穿过所述第二表面的导电通孔,所述第一和第二导电图案分别位于所述第一表面和所述第二表面上, 集成电路(IC)芯片在第一表面上并与第一导电图案电连接,测试焊盘与导电通孔重叠并且电连接到第一导电 图案和第二导电图案,并且外部连接图案在与导电通孔间隔开的第二表面上并电连接到第二导电图案。

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