公开(公告)号：US20240281282A1

公开(公告)日：2024-08-22

申请号：US18542792

申请日：2023-12-18

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Rui LI ,  Yajun HA

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A window-based dynamic scrubbing scheduling method is provided. By dynamically scheduling a user task and a scrubbing task, the method can reduce scrubbing conflicts of a field-programmable gate array (FPGA) scrubbing module and scrub each user task in a timely manner as much as possible. The method greatly reduces area and energy consumption overheads of a hardware circuit, and improves system reliability. The method proposes a negotiation-driven scrubbing scheduling algorithm and an integer linear programming (ILP)-based optimization-driven scrubbing scheduling algorithm. Based on global conflict information, the algorithms in the method can scrub more user tasks and improve the system reliability. The method ensures reliability of a mixed-criticality task set system. The method provides a dynamic voltage and frequency scaling (DVFS)-based multi-Internet Content Adaptation Protocol (ICAP) port allocation algorithm that can explore an impact of FPGA architecture support on the system reliability to further optimize the system reliability.

公开(公告)号：US20240273273A1

公开(公告)日：2024-08-15

申请号：US18401731

申请日：2024-01-02

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Guangyao YAN ,  Xinzhe LIU ,  Yajun HA ,  Hui WANG

IPC: G06F30/347 ,  G06F30/392 ,  G06F111/10 ,  G06F115/10

CPC classification number: G06F30/347 ,  G06F30/392 ,  G06F2111/10 ,  G06F2115/10

Abstract: A disordered parallel maximum flow/minimum cut method implemented by an energy-efficient field-programmable gate array (FPGA) folds a single-layer large two-dimensional grid graph into a multi-layer small grid graph. The method enables a folding grid architecture to store and process a grid graph that is much larger than a processor array in size. The folding grid architecture endows a two-dimensional processor array with a degree of freedom in a vertical direction, such that the two-dimensional processor array can leverage a potential for parallel performance of the folding grid architecture based on the degree of freedom in the vertical direction. The folding grid architecture enables a small-sized processor array to have an ability to process a grid graph that is much larger than the small-sized processor array in size. In addition, based on axial symmetry of folding, the folding grid architecture can greatly reduce cross-boundary transmission of data in the processor array.

公开(公告)号：US20240231415A1

公开(公告)日：2024-07-11

申请号：US18224579

申请日：2023-07-21

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Weixiong JIANG ,  Yajun HA

IPC: G06F1/08 ,  G06F1/26 ,  H04B17/364

CPC classification number: G06F1/08 ,  G06F1/26 ,  H04B17/364

Abstract: An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.

公开(公告)号：US20240220770A1

公开(公告)日：2024-07-04

申请号：US18387463

申请日：2023-11-07

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Shen ZHANG ,  Xinzhe LIU ,  Yajun HA

IPC: G06N3/04 ,  G06N5/04 ,  G06N7/01

CPC classification number: G06N3/04 ,  G06N5/04 ,  G06N7/01

Abstract: A high-efficient quantization method for a deep probabilistic network achieves good result through hybrid quantization, structure reformulation, and type optimization. Firstly, for a directed acyclic graph (DAG) structure, all nodes in the DAG are clustered, and each node is quantized by a specific arithmetic type based on the clustering category, to obtain a preliminarily quantized deep probabilistic network. Secondly, the multi-in nodes in a preliminarily quantized deep probabilistic network are reformulated based on the input weights, structural reformulation converts a multi-in node into a binary tree network containing only two-input nodes, and parametrical reformulation is performed on the reformulated structure. Finally, arithmetic types of all nodes are optimized by using an arithmetic type search method based on power consumption analysis and network accuracy analysis. The method can significantly reduce computational complexity and energy consumption for computing while maintaining model accuracy of the deep probabilistic network.

公开(公告)号：US20240112443A1

公开(公告)日：2024-04-04

申请号：US17798898

申请日：2021-09-22

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Xinzhe LIU ,  Guangyao YAN ,  Yajun HA

IPC: G06V10/762 ,  G06V10/764 ,  G06V10/96

CPC classification number: G06V10/7635 ,  G06V10/764 ,  G06V10/96

Abstract: A max-flow/min-cut solution algorithm for early terminating a push-relabel algorithm is provided. The max-flow/min-cut solution algorithm is used for an application that does not require an exact maximum flow, and includes: defining an early termination condition of the push-relabel algorithm by a separation condition and a stable condition; determining that the separation condition is satisfied if there is no source node s, s∈S, in the set T at any time in an operation process of the push-relabel algorithm; determining that the stable condition is satisfied if there is no active node in the set T; and terminating the push-relabel algorithm if both the separation condition and the stability condition are satisfied. The early termination technique is proposed to greatly reduce redundant computations and ensure that the algorithm terminates correctly in all cases.

公开(公告)号：US20230194602A1

公开(公告)日：2023-06-22

申请号：US17801266

申请日：2021-09-22

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Weixiong JIANG ,  Yajun HA

IPC: G01R31/317

CPC classification number: G01R31/31725

Abstract: A full-path circuit delay measurement device for a field-programmable gate array (FPGA) and a measurement method are provided. The measurement device includes two shadow registers and a phase-shifted clock, where the two shadow registers take an output of a measured combinational logic circuit as a clock and sample the phase-shifted clock SCLK as data; the two shadow registers are respectively triggered on rising and falling edges of the output of the measured combinational logic circuit to sample the phase-shifted clock; outputs of the two shadow registers are delivered by an OR gate as an input into a synchronization register; a clock of the synchronization register serves as a clock MCLK of the measured combinational logic circuit; an output of the synchronization register serves as that of the circuit delay measurement device; the phase-shifted clock SCLK and the clock MCLK of the measured combinational logic circuit have the same frequency.

公开(公告)号：US20230161627A1

公开(公告)日：2023-05-25

申请号：US18098746

申请日：2023-01-19

Applicant: SHANGHAITECH UNIVERSITY

Inventor： Hongtu ZHANG ,  Yuhao SHU ,  Yajun HA

IPC: G06F9/50 ,  G06F7/523 ,  G06F7/50 ,  H03K19/21

CPC classification number: G06F9/5027 ,  G06F7/523 ,  G06F7/50 ,  H03K19/21

Abstract: A high-energy-efficiency binary neural network accelerator applicable to artificial intelligence Internet of Things is provided. 0.3-0.6V sub/near threshold 10T1C multiplication bit units with series capacitors are configured for charge domain binary convolution. An anti-process deviation differential voltage amplification array between bit lines and DACs is configured for robust pre-amplification in 0.3V batch standardized operations. A lazy bit line reset scheme further reduces energy, and inference accuracy losses can be ignored. Therefore, a binary neural network accelerator chip based on in-memory computation achieves peak energy efficiency of 18.5 POPS/W and 6.06 POPS/W, which are respectively improved by 21× and 135× compared with previous macro and system work [9, 11].