公开(公告)号：US20210313288A1

公开(公告)日：2021-10-07

申请号：US17014349

申请日：2020-09-08

申请人： SK hynix Inc.

发明人： Sung Lae OH

IPC分类号： H01L23/00 ,  H01L25/18 ,  G11C16/08 ,  G11C16/24

摘要： A semiconductor memory device includes first column line pads, having a longer width and a shorter width, defined on one surface of a cell wafer, and coupled to a memory cell array of the cell wafer; second column line pads, having a longer width and a shorter width, defined on one surface of a peripheral wafer that is bonded to the one surface of the cell wafer, coupled to a page buffer circuit of the peripheral wafer, and bonded respectively to the first column line pads; first row line pads defined on the one surface of the cell wafer, and coupled to the memory cell array; and second row line pads defined on the one surface of the peripheral wafer, coupled to a row decoder of the peripheral wafer, and bonded respectively to the first row line pads. The longer widths of the first and second column line pads and the longer widths of the first and second row line pads extend in the same direction.

公开(公告)号：US20210287982A1

公开(公告)日：2021-09-16

申请号：US17079267

申请日：2020-10-23

申请人： SK hynix Inc.

发明人： Dong Hyuk KIM ,  Sung Lae OH ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11578 ,  H01L27/11573

摘要： A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.

公开(公告)号：US20210249087A1

公开(公告)日：2021-08-12

申请号：US16926202

申请日：2020-07-10

申请人： SK hynix Inc.

发明人： Sung Lae OH

IPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/24

摘要： A semiconductor memory device includes a plurality of first sub-blocks defined in a first memory chip; and a plurality of second sub-blocks defined in a second memory chip that is stacked on the first memory chip in a stack direction. Each of a plurality of memory blocks includes one of the plurality of first sub-blocks and one of the plurality of second sub-blocks, and wherein an erase voltage is separately applied to the first memory chip and the second memory chip in an erase operation, and the erase operation is performed in a sub-block.

公开(公告)号：US20210151466A1

公开(公告)日：2021-05-20

申请号：US17162333

申请日：2021-01-29

申请人： SK hynix Inc.

发明人： Sung Lae OH

IPC分类号： H01L27/11582 ,  G11C7/18 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

摘要： A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate defined with a cell area and a connection area in a first direction; a vertical channel passing through the electrode structure in the cell area; a hard mask pattern disposed on the electrode structure in the connection area, and having a plurality of opening holes; a plurality of contact holes defined in the electrode structure under the opening holes, and exposing pad areas of the electrode layers; and a slit dividing the hard mask pattern into units smaller than the electrode structure in the connection area.

公开(公告)号：US20210074367A1

公开(公告)日：2021-03-11

申请号：US16810774

申请日：2020-03-05

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： G11C16/26 ,  G11C16/04 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G06F12/0895

摘要： A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.

公开(公告)号：US20210057360A1

公开(公告)日：2021-02-25

申请号：US16811481

申请日：2020-03-06

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK

IPC分类号： H01L23/00 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  G06F3/06

摘要： A semiconductor memory device includes: a plurality of page buffers disposed on a substrate; and a plurality of pads exposed to one surface of a dielectric layer covering the page buffers, and coupled to the respective page buffers. The substrate comprises a plurality of high voltage regions and a plurality of low voltage regions which are alternately disposed in a second direction crossing a first direction. Each of the plurality of page buffers comprises a sensing unit and a bit line select transistor coupled between the sensing unit and the one of the plurality of pads. The bit line select transistors of the plurality of page buffers are disposed in the plurality of high voltage regions, and the plurality of pads are distributed and disposed in a plurality of pad regions which correspond to the high voltage regions and are spaced apart from each other in the second direction.

公开(公告)号：US20210020654A1

公开(公告)日：2021-01-21

申请号：US16723460

申请日：2019-12-20

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/311 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11573

摘要： A semiconductor memory device includes a stack disposed over a substrate defined with cell and connection areas; channel structures passing through the stack in the cell area; and slits defined in the stack. The stack includes first dielectric layers separately staked in the cell and connection areas; electrode layers disposed alternately with the first dielectric layers in the cell area and a periphery of the connection area adjacent to the slits; and second dielectric layers disposed alternately with the first dielectric layers in a central part of the connection area distant from the slits. A distance between the slits in the connection area is larger than a distance between the slits in the cell area, and, at a boundary between the periphery and the central part of the connection area, the electrode layers and the second dielectric layers disposed at the same layers are in contact with each other.

公开(公告)号：US20160111361A1

公开(公告)日：2016-04-21

申请号：US14667397

申请日：2015-03-24

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Jin Ho KIM

IPC分类号： H01L23/528 ,  H01L21/3213 ,  H01L27/115 ,  H01L21/768

CPC分类号： H01L27/11578 ,  H01L21/32139 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： A 3D nonvolatile memory device including memory cells vertically stacked is disclosed. Word lines are integrally formed to be elongated over adjacent cell regions spaced apart from each other, and portions of the word lines between the cell regions are partially etched in a stepped shape to form word line contact regions.

摘要翻译： 公开了一种包括垂直堆叠的存储单元的3D非易失性存储器件。 字线一体地形成为在彼此间隔开的相邻单元区域上延伸，并且单元区域之间的字线的部分被部分地蚀刻成台阶形状以形成字线接触区域。

公开(公告)号：US20230268379A1

公开(公告)日：2023-08-24

申请号：US17867084

申请日：2022-07-18

申请人： SK hynix Inc.

发明人： Hyun Soo SHIN ,  Sung Lae OH

IPC分类号： H01L49/02 ,  H01L27/11573

CPC分类号： H01L28/87 ,  H01L27/11573 ,  H01L28/88 ,  H01L28/91 ,  H01L27/11582

摘要： A semiconductor device includes a stack including a plurality of electrode layers which include a plurality of capacitor first electrode layers and a plurality of capacitor second electrode layers alternately stacked on a substrate and a plurality of dielectric layers which are disposed alternately with the plurality of electrode layers; a first conductive pillar passing through the stack and coupled to the plurality of capacitor first electrode layers; a second conductive pillar passing through the stack and coupled to the plurality of capacitor second electrode layers; and a plurality of insulation layer patterns insulating the first conductive pillar and the plurality of capacitor second electrode layers from each other and insulating the second conductive pillar and the plurality of capacitor first electrode layers from each other.

公开(公告)号：US20230268279A1

公开(公告)日：2023-08-24

申请号：US18309781

申请日：2023-04-29

申请人： SK hynix Inc.

发明人： Sung Lae OH

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H10B43/27

CPC分类号： H01L23/5384 ,  H01L25/0657 ,  H01L23/5386 ,  H01L29/0649 ,  H01L21/76802 ,  H01L21/762 ,  H10B43/27

摘要： A method for manufacturing a semiconductor device comprises: forming isolation layers in a front surface of an upper wafer substrate; forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate; forming a first dielectric layer that fills the through hole; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer; and forming a second wiring line coupled to the through via.