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    THREE-DIMENSIONAL (3D) NON-VOLATILE MEMORY DEVICE
    1.
    发明申请
    THREE-DIMENSIONAL (3D) NON-VOLATILE MEMORY DEVICE 有权
    三维（3D）非易失性存储器件

    公开(公告)号：US20160020221A1

    公开(公告)日：2016-01-21

    申请号：US14615368

    申请日：2015-02-05

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Go Hyun LEE ,  Chang Man SON ,  Soo Nam JUNG

    IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/10 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/792

    摘要： A three-dimensional (3D) non-volatile semiconductor memory device including a U-shaped channel structure is disclosed. The 3D non-volatile semiconductor memory device includes a pipe gate, an upper pipe channel disposed in the pipe gate at a first depth, a first lower pipe channel disposed in the pipe gate at a second depth different from the first depth, and neighboring the upper pipe channel in a first direction, and a second lower pipe channel disposed in the pipe gate at the second depth, and neighboring the upper pipe channel in a second direction perpendicular to the first direction, wherein the upper pipe channel and the lower pipe channels have the same length.

    摘要翻译： 公开了一种包括U形通道结构的三维（3D）非易失性半导体存储器件。 3D非挥发性半导体存储器件包括管道浇口，在第一深度处设置在管道浇口中的上部管道通道，以与第一深度不同的第二深度设置在管道浇口中的第一下部管道通道， 上管道在第一方向上，第二下管道在第二深度设置在管浇口中，并且在垂直于第一方向的第二方向上与上管道相邻，其中上管道和下管道 具有相同的长度。

    SEMICONDUCTOR DEVICE INCLUDING PAGE BUFFER
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING PAGE BUFFER 有权

    公开(公告)号：US20210241835A1

    公开(公告)日：2021-08-05

    申请号：US16932522

    申请日：2020-07-17

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

    IPC分类号： G11C16/24

    摘要： A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150243673A1

    公开(公告)日：2015-08-27

    申请号：US14448832

    申请日：2014-07-31

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Go Hyun LEE ,  Chang Man SON ,  Soo Nam JUNG

    IPC分类号： H01L27/115 ,  G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  H01L29/792 ,  G11C5/06

    CPC分类号： H01L27/11582 ,  G11C5/063 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11573 ,  H01L29/7926

    摘要： Provided are a semiconductor device. The semiconductor device includes a memory block including a drain select line, word lines, and a source select line, which are spaced apart from one another and stacked in a direction perpendicular to a semiconductor substrate; and a peripheral circuit including a switching device connected to a bit line, which is disposed under a vertical channel layer vertically passing through the drain select line, the word lines, and the source select line.

    摘要翻译： 提供半导体器件。 该半导体器件包括一个包括漏极选择线，字线和源极选择线的存储块，它们彼此间隔开并沿垂直于半导体衬底的方向堆叠; 以及外围电路，其包括连接到位线的开关器件，所述开关器件设置在垂直通过所述漏极选择线，所述字线和所述源选择线的垂直沟道层下方。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING PAGE BUFFERS
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING PAGE BUFFERS 有权

    公开(公告)号：US20210217479A1

    公开(公告)日：2021-07-15

    申请号：US16885192

    申请日：2020-05-27

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Dong Hyuk KIM ,  Tae Sung PARK ,  Soo Nam JUNG

    IPC分类号： G11C16/24 ,  G11C16/04 ,  G11C16/26

    摘要： A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.

    SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE INCLUDING UNIT PAGE BUFFER BLOCKS HAVING FOUR PAGE BUFFER PAIRS 审中-公开

    公开(公告)号：US20230401157A1

    公开(公告)日：2023-12-14

    申请号：US18053003

    申请日：2022-11-07

    申请人： SK hynix Inc.

    发明人： Dong Hyuk KIM ,  Tae Sung PARK ,  Sang Hyun SUNG ,  Sung Lae OH ,  Soo Nam JUNG

    IPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/123

    CPC分类号： G06F12/0895 ,  G06F12/0882 ,  G06F12/125

    摘要： A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.