公开(公告)号：US10706927B1

公开(公告)日：2020-07-07

申请号：US16407100

申请日：2019-05-08

Applicant: SK hynix Inc.

Inventor： Seok-Man Hong ,  Tae-Hoon Kim

IPC: G11C13/00

Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.

公开(公告)号：US10509720B2

公开(公告)日：2019-12-17

申请号：US15628840

申请日：2017-06-21

Applicant: SK hynix Inc.

Inventor： Tae-Hoon Kim

IPC: G06F12/02 ,  H03K19/003 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G06F11/10 ,  G11C29/04

Abstract: An apparatus may include: a memory device suitable for writing data while erasing at least one monitor cell among a plurality of memory cells in a write mode, and reading the at least one monitor cell by supplying a monitor voltage in a monitor mode; and a controller suitable for transmitting a monitor command and address information for reading the at least one monitor cell to the memory device in the monitor mode, and determining whether to perform a reclaim operation based on the values of the at least one monitor cell read by the memory device.

公开(公告)号：US09984748B1

公开(公告)日：2018-05-29

申请号：US15604474

申请日：2017-05-24

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Lee ,  Woo-Tae Lee ,  Hyun-Jeong Kim ,  Myoung-Sub Kim ,  Tae-Hoon Kim

IPC: G11C11/00 ,  G11C13/00 ,  G06F3/06 ,  G11C13/04

CPC classification number: G11C13/004 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C13/047 ,  G11C2013/0042

Abstract: A semiconductor memory includes a cell array including a plurality of resistive memory cells arranged in a plurality of columns and a plurality of rows, the plurality of resistive memory cells having a snapback characteristic; and a read circuit configured to apply a read voltage to a memory cell selected among the plurality of resistive memory cells, and sense data stored in the selected memory cell by determining whether or not a snapback phenomenon has occurred in the selected memory cell, wherein the read voltage has a level higher than a level of a first voltage and lower than a level of a second voltage, wherein the snapback phenomenon occurs when the first voltage is applied to the selected memory cell in a case where the selected memory cell stores first data, and wherein the snapback phenomenon occurs when the second voltage is applied to the selected memory cell in a case where the selected memory cell stores second data.

公开(公告)号：US09825082B2

公开(公告)日：2017-11-21

申请号：US14850624

申请日：2015-09-10

Applicant: SK hynix Inc.

Inventor： Tae-Hoon Kim ,  Woong-Hee Lee

IPC: H01L27/00 ,  H01L27/146 ,  H04N5/369 ,  H04N5/378

CPC classification number: H01L27/14641 ,  H01L27/14645 ,  H04N5/3698 ,  H04N5/378

Abstract: Disclosed are a pixel amplification apparatus and a CMOS image sensor thereof. The pixel amplification apparatus includes a pixel bias sampling unit that samples a first pixel bias voltage, a pixel bias current supply unit that supplies an output node of a pixel signal with a first pixel bias current based on a sampled bias voltage outputted from the pixel bias sampling unit, and a pixel bias current adding unit that additionally supplies the output node with a second pixel bias current in response to a second pixel bias voltage and a period control signal.

公开(公告)号：US11450360B2

公开(公告)日：2022-09-20

申请号：US17119821

申请日：2020-12-11

Applicant: SK hynix Inc.

Inventor： Seok-Man Hong ,  Myoung-Sub Kim ,  Tae-Hoon Kim

IPC: G11C7/22 ,  G11C7/10 ,  G11C13/00

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.

公开(公告)号：US11017855B2

公开(公告)日：2021-05-25

申请号：US16890753

申请日：2020-06-02

Applicant: SK hynix Inc.

Inventor： Seok-Man Hong ,  Tae-Hoon Kim

IPC: G11C13/00

Abstract: An operating method of an electronic device including a semiconductor memory, the operating method includes selecting one of a plurality of memory cells during a set operation, applying a write current having a slow quenching pattern to the selected memory cell, monitoring a cell current flowing through the selected memory cell, generating a discharge control signal corresponding to a result of the monitoring, and discharging the write current in response to the discharge control signal.

公开(公告)号：US10678633B2

公开(公告)日：2020-06-09

申请号：US16196928

申请日：2018-11-20

Applicant: SK hynix Inc.

Inventor： Tae-Hoon Kim

IPC: G11C16/04 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  H03M13/09

Abstract: A memory system includes a controller configured to transfer first data for a program operation, and a memory device configured to perform an error check operation for determining whether second data received from the controller are equal to the first data and the program operation for storing the first data.

公开(公告)号：US10553296B2

公开(公告)日：2020-02-04

申请号：US16157710

申请日：2018-10-11

Applicant: SK hynix Inc.

Inventor： Tae-Hoon Kim

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C11/56 ,  G11C16/04

Abstract: A memory device includes a memory cell array including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines; a read/write circuit including a plurality of page buffers coupled to the plurality of bit lines; a power supply circuit suitable for generating voltages to be applied to the memory cell array and the read/write circuit; and a control circuit suitable for receiving a read command and an address signal from an external device, and controlling the memory cell array, the read/write circuit and the power supply circuit based on the read command and the address signal.

公开(公告)号：US20190335128A1

公开(公告)日：2019-10-31

申请号：US16219246

申请日：2018-12-13

Applicant: SK hynix Inc.

Inventor： Hyeon-June Kim ,  Tae-Hoon Kim ,  Hyun-Mook Park

IPC: H04N5/3745 ,  H04N5/378 ,  H04N5/376 ,  H04N5/357 ,  H04N9/04 ,  H01L27/146

Abstract: Provided are a comparison device that may minimize an influence of banding noise by offsetting the banding noise, and a CMOS image sensor including the comparison device. The comparison device may include a comparison circuit configured to compare a pixel signal and a ramp signal with each other and output a comparison signal, a banding noise adjustment circuit coupled to the comparison circuit to adjust electrical characteristic values of the comparison circuit, a banding value generation circuit coupled to the banding noise adjustment circuit to provide the banding noise adjustment circuit with a banding value generated based on a setting code value, and a banding noise reduction circuit coupled to the banding noise adjustment circuit and configured to reduce the banding noise of the comparison circuit by adjusting electrical characteristic values of the comparison circuit.

公开(公告)号：US10431267B2

公开(公告)日：2019-10-01

申请号：US15824626

申请日：2017-11-28

Applicant: SK hynix Inc.

Inventor： Seok-Man Hong ,  Tae-Hoon Kim

IPC: G11C7/10 ,  G11C11/404 ,  H01L27/22 ,  G11C11/407 ,  G11C16/26 ,  G11C13/00 ,  G11C11/56 ,  G11C7/06 ,  G11C29/02

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.