公开(公告)号：US10861503B1

公开(公告)日：2020-12-08

申请号：US16698802

申请日：2019-11-27

Applicant: SK hynix Inc.

Inventor： Myoung-Sub Kim ,  Tae-Hoon Kim ,  Hye-Jung Choi ,  Seok-Man Hong

IPC: G11C5/02 ,  H01L27/22 ,  G11C13/00 ,  H01L27/108

Abstract: A semiconductor memory includes: a first line; a second line; a third line; a first memory cell disposed between the first line and the second line at an intersection region of the first line and the second line, the first memory cell including a first selection element layer and a first electrode coupled to the first selection element layer; and a second memory cell disposed between the second line and the third line at an intersection region of the second line and third second line, the second memory cell including a second selection element layer and a second electrode coupled to the second selection element layer. A threshold voltage of the first selection element layer is greater than a threshold voltage of the second selection element layer, and a resistance of the second electrode is greater than a resistance of the first electrode.

公开(公告)号：US11450360B2

公开(公告)日：2022-09-20

申请号：US17119821

申请日：2020-12-11

Applicant: SK hynix Inc.

Inventor： Seok-Man Hong ,  Myoung-Sub Kim ,  Tae-Hoon Kim

IPC: G11C7/22 ,  G11C7/10 ,  G11C13/00

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.

公开(公告)号：US10283197B1

公开(公告)日：2019-05-07

申请号：US15669758

申请日：2017-08-04

Applicant: SK hynix Inc.

Inventor： Myoung-Sub Kim ,  Seok-Man Hong ,  Tae-Hoon Kim

IPC: G11C13/00 ,  G06F3/06

Abstract: A method for reading a data of a memory cell comprising a selection device and a resistive memory device which has a high resistance state or a low resistance state according to a data stored therein includes: applying a first read voltage to the memory cell; applying a second read voltage to the memory cell, the second read voltage having a level lower than a level of the first read voltage; and sensing the data of the memory cell while the second read voltage is applied to the memory cell.

公开(公告)号：US11170824B2

公开(公告)日：2021-11-09

申请号：US17088334

申请日：2020-11-03

Applicant: SK hynix Inc.

Inventor： Myoung-Sub Kim ,  Tae-Hoon Kim ,  Hye-Jung Choi ,  Seok-Man Hong

IPC: G11C5/02 ,  H01L27/22 ,  G11C13/00 ,  H01L27/108

Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.

公开(公告)号：US10090029B2

公开(公告)日：2018-10-02

申请号：US15638201

申请日：2017-06-29

Applicant: SK hynix Inc.

Inventor： Myoung-Sub Kim

IPC: G11C8/00 ,  G11C7/12 ,  G11C11/16 ,  G11C13/04 ,  G11C13/00

Abstract: An electronic device includes a semiconductor memory that includes: a memory cell coupled between first and second lines and having a specific resistance state; a first read circuit suitable for supplying a predetermined pattern of a read voltage to the first line to generate a cell current corresponding to the specific resistance state of the memory cell during a read operation mode; and a second read circuit suitable for generating read data based on the cell current flowing through the second line during the read operation mode.

公开(公告)号：US09984748B1

公开(公告)日：2018-05-29

申请号：US15604474

申请日：2017-05-24

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Lee ,  Woo-Tae Lee ,  Hyun-Jeong Kim ,  Myoung-Sub Kim ,  Tae-Hoon Kim

IPC: G11C11/00 ,  G11C13/00 ,  G06F3/06 ,  G11C13/04

CPC classification number: G11C13/004 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C13/047 ,  G11C2013/0042

Abstract: A semiconductor memory includes a cell array including a plurality of resistive memory cells arranged in a plurality of columns and a plurality of rows, the plurality of resistive memory cells having a snapback characteristic; and a read circuit configured to apply a read voltage to a memory cell selected among the plurality of resistive memory cells, and sense data stored in the selected memory cell by determining whether or not a snapback phenomenon has occurred in the selected memory cell, wherein the read voltage has a level higher than a level of a first voltage and lower than a level of a second voltage, wherein the snapback phenomenon occurs when the first voltage is applied to the selected memory cell in a case where the selected memory cell stores first data, and wherein the snapback phenomenon occurs when the second voltage is applied to the selected memory cell in a case where the selected memory cell stores second data.

公开(公告)号：US10056138B1

公开(公告)日：2018-08-21

申请号：US15605661

申请日：2017-05-25

Applicant: SK hynix Inc.

Inventor： Hyun-Jeong Kim ,  Myoung-Sub Kim ,  Tae-Hoon Kim ,  Seung-Hwan Lee ,  Woo-Tae Lee

IPC: G11C11/00 ,  G11C13/00 ,  G06F3/06

CPC classification number: G11C13/0026 ,  G11C8/10 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/2253 ,  G11C11/2255 ,  G11C11/2257 ,  G11C13/0023 ,  G11C13/0028

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include a memory region comprising a plurality of memory cells disposed at respective intersections between a plurality of row lines and a plurality of column lines, the plurality of row lines extending in a first direction, the plurality of column lines extending in a second direction crossing the first direction; first and second row drivers arranged on one side and the other side of the memory region in the first direction, respectively, and driving a common row line corresponding to a row address among the plurality of row lines; and a column driver driving a common column line corresponding to a column address among the plurality of column lines, wherein the first and second row drivers are coupled to the common row line.

公开(公告)号：US10547001B2

公开(公告)日：2020-01-28

申请号：US15878257

申请日：2018-01-23

Applicant: SK hynix Inc.

Inventor： Dae-Gun Kang ,  Su-Jin Chae ,  Sung-Kyu Min ,  Myoung-Sub Kim ,  Chi-Ho Kim ,  Su-Yeon Lee

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.

公开(公告)号：US10373679B1

公开(公告)日：2019-08-06

申请号：US15604562

申请日：2017-05-24

Applicant: SK hynix Inc.

Inventor： Woo-Tae Lee ,  Seok-Man Hong ,  Myoung-Sub Kim ,  Tae-Hoon Kim ,  Hyun-Jeong Kim

IPC: G06F3/06 ,  G11C13/00 ,  G11C13/04

Abstract: A method for reading data of a memory cell including a resistive memory element having a low resistance state and a high resistance state according to stored data and a selection element may include applying a recovery voltage to both ends of the memory cell, and applying a read voltage to both ends of the memory cell and sensing the data. The recovery voltage may be equal to or more than a second voltage obtained by adding a drift value of the memory cell to a first voltage for turning on the memory cell in a case in which the resistive memory element is in the low resistance state.

公开(公告)号：US09842882B1

公开(公告)日：2017-12-12

申请号：US15451215

申请日：2017-03-06

Applicant: SK hynix Inc.

Inventor： Myoung-Sub Kim ,  Hyun-Jeong Kim ,  Woo-Tae Lee

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/1233 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078 ,  H01L23/528 ,  H01L27/2418 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A semiconductor memory includes first to third lines, the second line crossing the first and third lines between the first line and the third line, a first memory element overlapping an intersection region of the first and second lines between the first line and the second line, the first memory element including a first memory layer, a first electrode under the first memory layer, and a second electrode over the first memory layer, and a second memory element overlapping an intersection region of the second and third lines between the second line and the third line, the second memory element including a second memory layer, a third electrode under the second memory layer, and a fourth electrode over the second memory layer. An electrical resistance relation of the third and fourth electrodes is controlled according to an electrical resistance relation of electrical resistances of the first and second electrodes.