公开(公告)号：US20210210468A1

公开(公告)日：2021-07-08

申请号：US17210743

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Hirotaka TAKENO ,  Wenzhen WANG ,  Atsushi OKAMOTO

IPC: H01L25/065 ,  H01L27/02

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US20190393206A1

公开(公告)日：2019-12-26

申请号：US16438026

申请日：2019-06-11

Applicant: SOCIONEXT INC.

Inventor： Wenzhen WANG ,  Hirotaka TAKENO ,  Atsushi OKAMOTO

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

公开(公告)号：US20160005450A1

公开(公告)日：2016-01-07

申请号：US14755935

申请日：2015-06-30

Applicant: SOCIONEXT INC.

Inventor： Hirotaka TAKENO ,  Akio YAMAMOTO

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/3562 ,  H03K19/18

Abstract: A data holding circuit includes: a latch circuit having a first terminal and a second terminal, a logical value held at the first terminal being changed according to a value to be held by the data holding circuit, and the second terminal holding an inverted logical value of the logical value held at the first terminal; and a storing circuit which stores the logical values held at the first terminal and the second terminal in response to a write signal, and sets the logical values held at the first terminal and the second terminal to the stored logical values in response to a read signal, wherein the storing circuit includes two Magnetic Tunnel Junction elements which are connected in series between the first terminal and the second terminal and in reverse directions to each other.

Abstract translation: 数据保持电路包括：具有第一端子和第二端子的锁存电路，保持在第一端子处的逻辑值根据由数据保持电路保持的值而改变，第二端子保持反相逻辑值 在第一个终端持有的逻辑价值; 以及存储电路，其响应于写信号存储保持在第一终端和第二终端的逻辑值，并且响应于读信号将保持在第一终端和第二终端的逻辑值设置为存储的逻辑值 其中，所述存储电路包括串联连接在所述第一端子和所述第二端子之间并且彼此相反方向的两个磁隧道结元件。