公开(公告)号：US20210272904A1

公开(公告)日：2021-09-02

申请号：US17322570

申请日：2021-05-17

申请人： SOCIONEXT INC.

发明人： Hideyuki KOMURO ,  Junji IWAHORI

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L23/535

摘要： A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

公开(公告)号：US20210028191A1

公开(公告)日：2021-01-28

申请号：US17065875

申请日：2020-10-08

申请人： SOCIONEXT INC.

发明人： Toshio HINO ,  Junji IWAHORI

IPC分类号： H01L27/118 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02

摘要： The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

公开(公告)号：US20200303501A1

公开(公告)日：2020-09-24

申请号：US16897809

申请日：2020-06-10

申请人： SOCIONEXT INC.

发明人： Junji IWAHORI

IPC分类号： H01L29/06 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78

摘要： A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.

公开(公告)号：US20190371819A1

公开(公告)日：2019-12-05

申请号：US16543220

申请日：2019-08-16

申请人： SOCIONEXT INC.

发明人： Junji IWAHORI

IPC分类号： H01L27/118

摘要： In a semiconductor integrated circuit device using three-dimensional transistor devices, a delay cell having a large delay value per unit area is implemented. A first cell, which is a logic cell, includes three-dimensional transistor devices. A second cell, which is a delay cell, includes three-dimensional transistor devices. The length by which a second local interconnect protrudes from a second solid diffusion layer portion in a direction away from a power supply interconnect in the second cell is greater than the length by which a first local interconnect protrudes from a first solid diffusion layer portion in a direction away from the power supply interconnect in the first cell.

公开(公告)号：US20190123063A1

公开(公告)日：2019-04-25

申请号：US16228319

申请日：2018-12-20

申请人： SOCIONEXT INC.

发明人： Toshio HINO ,  Junji IWAHORI

IPC分类号： H01L27/118 ,  H01L27/02

摘要： A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US20170194329A1

公开(公告)日：2017-07-06

申请号：US15205421

申请日：2016-07-08

申请人： SOCIONEXT INC.

发明人： Junji IWAHORI

IPC分类号： H01L27/11 ,  H01L27/088 ,  H01L23/528

CPC分类号： H01L27/1104 ,  H01L23/5286 ,  H01L27/0886 ,  H01L27/11582 ,  H01L28/00

摘要： A cell includes a plurality of fin transistors formed in a semiconductor substrate. In the cell, a fin serving as a source and drain of each of the plurality of fin transistors is arranged in plurality at a first pitch in a first direction. Moreover, the cell height that is the length in the first direction of the cell is an n multiple (n is an integer) of half the length of the first pitch. Wires are connected to the cell, and are arranged at a second pitch, which is a 1/m multiple (m is an integer) of the cell height in the first direction.