公开(公告)号：US20240113124A1

公开(公告)日：2024-04-04

申请号：US18540220

申请日：2023-12-14

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  B82Y10/00 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/11807 ,  B82Y10/00 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L2027/11864 ,  H01L2027/11874

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US20220231681A1

公开(公告)日：2022-07-21

申请号：US17577701

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Junji IWAHORI

IPC: H03K17/16

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US20200350439A1

公开(公告)日：2020-11-05

申请号：US16931693

申请日：2020-07-17

Applicant: SOCIONEXT INC.

Inventor： Junji IWAHORI

IPC: H01L29/786 ,  H01L27/088

Abstract: A semiconductor integrated circuit device provided with vertical nanowire (VNW) FETs includes a tap cell. The tap cell includes a power supply interconnect extending in a first direction and a bottom region of a first conductivity type formed in a top portion of a well or substrate of the first conductivity type. The bottom region overlaps the power supply interconnect as viewed from top and is connected with the power supply interconnect.

公开(公告)号：US20250040236A1

公开(公告)日：2025-01-30

申请号：US18911967

申请日：2024-10-10

Applicant: Socionext Inc.

Inventor： Junji IWAHORI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423

Abstract: A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.

公开(公告)号：US20230120959A1

公开(公告)日：2023-04-20

申请号：US18069084

申请日：2022-12-20

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Junji IWAHORI

IPC: H03K17/16 ,  H03K17/687

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US20220223588A1

公开(公告)日：2022-07-14

申请号：US17706117

申请日：2022-03-28

Applicant: Socionext Inc.

Inventor： Junji IWAHORI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234

Abstract: A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.

公开(公告)号：US20200286918A1

公开(公告)日：2020-09-10

申请号：US16881255

申请日：2020-05-22

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US20240332304A1

公开(公告)日：2024-10-03

申请号：US18738947

申请日：2024-06-10

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO ,  Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11881

Abstract: First and second semiconductor chips are stacked one upon the other with the back face of the first semiconductor chip opposed to the principal face of the second semiconductor chip. The first semiconductor chip includes: first and second power lines formed in a buried interconnect layer, extending in the X direction, and adjoining each other in the Y direction; first and second contacts provided between the first and second power lines and the chip back face; and a third contact provided between a signal line and the chip back face. The third contact is located between the first and second power lines in the Y direction, and at a position different from the positions of the first and second contacts in the X direction, in planar view.

公开(公告)号：US20220392999A1

公开(公告)日：2022-12-08

申请号：US17889106

申请日：2022-08-16

Applicant: Socionext Inc.

Inventor： Junji IWAHORI

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G11C11/412 ,  H01L27/11 ,  H01L27/118

Abstract: A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.

公开(公告)号：US20210242242A1

公开(公告)日：2021-08-05

申请号：US17235603

申请日：2021-04-20

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.