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公开(公告)号：US20190319157A1
公开(公告)日：2019-10-17
申请号：US16378153
申请日：2019-04-08
Inventor： Romain COFFY , Laurent HERARD , David GANI
IPC: H01L31/12 , H01L31/0203
Abstract: A carrier wafer has a back face and a front face and a network of electrical connections between the back face and the front face. A first electronic chip is mounted with its bottom face on top of the front face of the carrier wafer. The first electronic chip has a through-opening extending between the bottom face and a face. A second electronic chip is installed in the through-opening and mounted to the front face of the carrier wafer.
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公开(公告)号：US20230137239A1
公开(公告)日：2023-05-04
申请号：US17970336
申请日：2022-10-20
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Younes BOUTALEB , David KAIRE , Romain COFFY
IPC: H01L23/367 , H01L23/373 , H01L23/053 , H01L21/52
Abstract: The present description concerns an electronic device comprising: an electronic chip comprising an active area on a first surface, and a second surface opposite to the first surface; a substrate, the first surface of said chip being mounted on a third surface of said substrate; and a thermally-conductive cover comprising a transverse portion extending at least above the second surface of said electronic chip, wherein the electronic device further comprises at least one thermally-conductive pillar coupling the second surface of the electronic chip to said transverse portion of said thermally-conductive cover.
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公开(公告)号：US20220376379A1
公开(公告)日：2022-11-24
申请号：US17742039
申请日：2022-05-11
Inventor： Romain COFFY , Georg KIMMICH
Abstract: A package includes an upper level mounted to a lower level. The upper level includes a stack formed by insulating layers and conductive elements and includes a first conductive track of an antenna. A plastic element rests on the stack. A first cavity is defined in the plastic element. A second conductive track of the antenna is located on a wall of the plastic element (for example, in or adjacent to the first cavity). A second cavity is also defined in the plastic element surrounding the first cavity. A third conductive track of the antenna is located on a wall of the plastic element (for example, in the second cavity). A third cavity is delimited between the upper and lower levels and an integrated circuit chip is mounted within the third cavity and electrically connected to the antenna.
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公开(公告)号：US20220196938A1
公开(公告)日：2022-06-23
申请号：US17546314
申请日：2021-12-09
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain COFFY , Jean-Michel RIVIERE
IPC: G02B6/42
Abstract: An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.
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公开(公告)号：US20220187123A1
公开(公告)日：2022-06-16
申请号：US17545369
申请日：2021-12-08
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain COFFY , Younes BOUTALEB
Abstract: An electronic chip supports an optical device and electric connection zones. An insulating coating coats the electronic chip, covers the electric connection zones and exposes the optical device. An optical plugging element is at least partly fastened onto a first face of the insulating coating and is optically coupled to the optical device. Vias pass through the insulating coating from its first face to a second face opposite to the first face. Inner walls of the vias support electrically conductive paths connected to the electric connection zones of the electronic chip by electrically conductive tracks arranged on the first face of the insulating coating. The electrically conductive paths of the vias further have ends protruding onto the second face of the insulating coating.
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Patent Agency Ranking
公开(公告)号：US20210242115A1
公开(公告)日：2021-08-05
申请号：US17165295
申请日：2021-02-02
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain COFFY , Fabien QUERCIA
IPC: H01L23/498 , H01L23/552 , H01L23/66 , H01L21/48 , H01L23/00 , H01Q1/22
Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.
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公开(公告)号：US20210066271A1
公开(公告)日：2021-03-04
申请号：US17006092
申请日：2020-08-28
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain COFFY , Remi BRECHIGNAC , Jean-Michel RIVIERE
IPC: H01L25/16 , H01L33/62 , H01L31/02 , H01L31/0203 , H01L33/52
Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.
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公开(公告)号：US20200312735A1
公开(公告)日：2020-10-01
申请号：US16829210
申请日：2020-03-25
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain COFFY , Alexandre COULLOMB , Olivier FRANIATTE
IPC: H01L23/367 , H01L21/48 , H01L23/373 , H01L23/49
Abstract: A substrate includes a through cavity. A heat sink is mounted so as to close one end of the through cavity. An integrated circuit (IC) chip is also mounted in the cavity. Conductive wires provide an electrical connection between pads on an upper surface of the IC chip and metallizations on the substrate. The mounted heat sink is positioned within the substrate in one implementation and positioned mounted to a back surface of the substrate in another implementation.
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公开(公告)号：US20200072446A1
公开(公告)日：2020-03-05
申请号：US16552419
申请日：2019-08-27
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Romain COFFY , Jean-Michel RIVIERE
Abstract: The present disclosure relates to a light-emitting device comprising: a light source mounted on a substrate; a wire for providing a supply voltage or activation signal to the light source, a cap covering the light source and having a diffuser adapted to diffuse light generated by the light source; and either: a volume of glue fixing an intermediate section of the wire to the cap; or an arm fixed to the cap and extending between the intermediate section of the wire and the substrate.
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公开(公告)号：US20200033537A1
公开(公告)日：2020-01-30
申请号：US16519753
申请日：2019-07-23
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Romain COFFY , Florian PERMINJAT , Jean-Michel RIVIERE
IPC: G02B6/30
Abstract: An electronic chip includes an integrated optical-wave guide having an end section that extends parallel to a face of the electronic chip. A local groove provided in the electronic chip extends adjacent to the end section of the integrated optical-wave guide. An elongate optical cable includes an optical-wave guide and has an end portion that is at least partially engaged in the local groove. The end portion of the elongate optical cable is configured to support an optical coupling of the optical-wave guide to the integrated optical-wave guide via lateral coupling in a zone of the local groove. An exterior package is provided to house the electronic chip.
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