公开(公告)号：US20230245984A1

公开(公告)日：2023-08-03

申请号：US18128044

申请日：2023-03-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Denis FARISON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L23/576 ,  H01L21/563 ,  H01L23/528 ,  H01L24/09 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49112 ,  H01L2225/06555 ,  H01L2924/14 ,  H04L9/002

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

公开(公告)号：US20210066554A1

公开(公告)日：2021-03-04

申请号：US17006128

申请日：2020-08-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Remi BRECHIGNAC ,  Jean-Michel RIVIERE

IPC: H01L33/52 ,  H01L33/44 ,  H01L33/62 ,  H01L31/0216 ,  H01L31/0203

Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.

公开(公告)号：US20190139947A1

公开(公告)日：2019-05-09

申请号：US16182315

申请日：2018-11-06

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine SAXOD ,  Jean-Michel RIVIERE

IPC: H01L25/16 ,  H01L31/0203 ,  H01L31/0232 ,  H01L31/02 ,  H01L31/167 ,  H01L31/18 ,  H01L33/48 ,  H01L33/58 ,  H01L33/62 ,  H01L33/00 ,  B29C45/14 ,  B29C69/00

Abstract: An encapsulation cover for an electronic package includes a cover body having a frontal wall provided with at least one optical element allowing light to pass through. The optical element is inserted into the encapsulation cover by overmolding into a through-passage of the frontal wall. A front face of the optical element is set back with respect to a front face of the frontal wall. The process for fabricating the encapsulation cover includes forming a stack of a sacrificial spacer on top of an optical element, with the stack placed into a cavity of a mold.

公开(公告)号：US20240146019A1

公开(公告)日：2024-05-02

申请号：US18408149

申请日：2024-01-09

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Fabien QUERCIA ,  Jean-Michel RIVIERE

IPC: H01S5/02345 ,  H01L23/00

CPC classification number: H01S5/02345 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/12042 ,  H01L2924/18165

Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.

公开(公告)号：US20220029034A1

公开(公告)日：2022-01-27

申请号：US17495606

申请日：2021-10-06

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine SAXOD ,  Veronique FERRE ,  Agnes BAFFERT ,  Jean-Michel RIVIERE

IPC: H01L31/0203 ,  H01L21/56 ,  H01L31/0232 ,  H01L31/16

Abstract: An encapsulation cover for an electronic package includes a frontal wall with a through-passage extending between faces. The frontal wall includes an optical element that allows light to pass through the through-passage. A cover body and a metal insert that is embedded in the cover body, with the cover body being overmolded over the metal insert, defines at least part of the frontal wall.

公开(公告)号：US20190376676A1

公开(公告)日：2019-12-12

申请号：US16439308

申请日：2019-06-12

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Joseph HANNAN ,  Stuart ROBERTSON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: F21V23/04 ,  H05B33/08 ,  F21V23/00 ,  H01L33/44 ,  H01L23/00 ,  F21K9/20

Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a molded body having an opening permitting the passage of a light beam generated by the light source; one or more surfaces for receiving a diffuser; and first and second conducting pins traversing the molded body, each pin abutting one of said surfaces.

公开(公告)号：US20190356390A1

公开(公告)日：2019-11-21

申请号：US16409723

申请日：2019-05-10

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Alexandre COULLOMB ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H04B10/40 ,  H04B10/50 ,  H04B10/69 ,  H01L31/0203 ,  H01L25/04

Abstract: An optoelectronic device includes a substrate and a first optoelectronic chip flush with a surface of the substrate. The device includes a cover that covers the substrate and the first optoelectronic chip. The cover comprises a cavity above a first optical transduction region of the first optoelectronic chip. The device also includes a second optoelectronic chip having a second optical transduction region spaced apart from the first optical transduction region and the cavity continues above the second optical transduction region.

公开(公告)号：US20190355674A1

公开(公告)日：2019-11-21

申请号：US16411960

申请日：2019-05-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Denis FARISON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L25/065

Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

公开(公告)号：US20190267349A1

公开(公告)日：2019-08-29

申请号：US16282594

申请日：2019-02-22

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Marie-Astrid PIN ,  Karine SAXOD ,  Jean-Michel RIVIERE

IPC: H01L23/00 ,  H01L31/0203 ,  H01L33/48 ,  H01L21/78

Abstract: Individual electronic units are formed by cutting a collective assembly. A collective support plate is provided which includes electronic chips. A collective cover plate is provided which includes ribs defining recesses. The collective assembly is formed by mounting the collective cover plate to the collective support plate in a manner where the electronic chips are located in the recesses and the ribs are located between electronic chips. A bead of glue is interposed between ends of the ribs and the surface of the collective support plate. After the glue is hardened, a cutting operation is performed on the collective assembly by cutting through the ribs and the collective support plate to produce the individual electronic units.

公开(公告)号：US20220196938A1

公开(公告)日：2022-06-23

申请号：US17546314

申请日：2021-12-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain COFFY ,  Jean-Michel RIVIERE

IPC: G02B6/42

Abstract: An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.