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    COOLING OF AN ELECTRONIC DEVICE
    2.
    发明申请
    COOLING OF AN ELECTRONIC DEVICE 有权

    公开(公告)号：US20230140705A1

    公开(公告)日：2023-05-04

    申请号：US17970327

    申请日：2022-10-20

    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

    Inventor： Younes BOUTALEB ,  Romain COFFY

    IPC: H01L23/367 ,  H01L21/52 ,  H01L23/498

    Abstract: The present description concerns an electronic device comprising an electronic chip and a package for protecting said chip, said package comprising: a substrate comprising an alternation of electrically-insulating layers and of thermally-conductive layers where at least one electrically-insulating layer comprises at least a thermally-conductive portion; and a cover made of a thermally-conductive material comprising at least one lateral portion arranged in at least one cavity formed from a first surface of said substrate.

    COOLING OF AN ELECTRONIC DEVICE
    3.
    发明申请
    COOLING OF AN ELECTRONIC DEVICE 有权

    公开(公告)号：US20230137239A1

    公开(公告)日：2023-05-04

    申请号：US17970336

    申请日：2022-10-20

    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

    Inventor： Younes BOUTALEB ,  David KAIRE ,  Romain COFFY

    IPC: H01L23/367 ,  H01L23/373 ,  H01L23/053 ,  H01L21/52

    Abstract: The present description concerns an electronic device comprising: an electronic chip comprising an active area on a first surface, and a second surface opposite to the first surface; a substrate, the first surface of said chip being mounted on a third surface of said substrate; and a thermally-conductive cover comprising a transverse portion extending at least above the second surface of said electronic chip, wherein the electronic device further comprises at least one thermally-conductive pillar coupling the second surface of the electronic chip to said transverse portion of said thermally-conductive cover.

    OPTICAL PACKAGE
    4.
    发明申请
    OPTICAL PACKAGE 有权

    公开(公告)号：US20220357536A1

    公开(公告)日：2022-11-10

    申请号：US17735653

    申请日：2022-05-03

    Applicant: STMicroelectrnoics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

    Inventor： Deborah COGONI ,  Raphael GOUBOT ,  Younes BOUTALEB

    IPC: G02B6/42 ,  G02B6/43

    Abstract: An optical package includes a substrate made of a first material having an upper surface and a lower surface. The substrate further includes at least one cavity opening onto an upper surface of the substrate. Electrical connection vias extend through the substrate. An electronic integrated circuit chip is mounted on the upper surface of the substrate in a position so as to cover the at least one cavity. The electronic integrated circuit chip includes an integrated optical sensor. Each cavity is filled with a second material having a thermal conductivity greater than the thermal conductivity of the first material. The electrical connection vias are arranged on either side of each cavity and between two cavities.

    OPTICAL PACKAGE OF AN INTEGRATED CIRCUIT
    5.
    发明申请
    OPTICAL PACKAGE OF AN INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220187123A1

    公开(公告)日：2022-06-16

    申请号：US17545369

    申请日：2021-12-08

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Romain COFFY ,  Younes BOUTALEB

    IPC: G01J1/42 ,  H01L31/18

    Abstract: An electronic chip supports an optical device and electric connection zones. An insulating coating coats the electronic chip, covers the electric connection zones and exposes the optical device. An optical plugging element is at least partly fastened onto a first face of the insulating coating and is optically coupled to the optical device. Vias pass through the insulating coating from its first face to a second face opposite to the first face. Inner walls of the vias support electrically conductive paths connected to the electric connection zones of the electronic chip by electrically conductive tracks arranged on the first face of the insulating coating. The electrically conductive paths of the vias further have ends protruding onto the second face of the insulating coating.

    CHIP PACKAGE AND ITS METHOD OF FABRICATION
    6.
    发明公开
    CHIP PACKAGE AND ITS METHOD OF FABRICATION 审中-公开

    公开(公告)号：US20240162259A1

    公开(公告)日：2024-05-16

    申请号：US18388927

    申请日：2023-11-13

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Younes BOUTALEB ,  Julien CUZZOCREA

    IPC: H01L27/146 ,  H01L23/00

    CPC classification number: H01L27/14618 ,  H01L24/48 ,  H01L27/14683 ,  H01L2224/48091 ,  H01L2224/48227

    Abstract: A method of fabricating a package for an integrated circuit chip, includes: a) mounting the integrated circuit chip to a support; b) forming a first resist layer over the integrated circuit chip which has a first opening emerging onto a central portion of the integrated circuit chip; c) forming a second resist layer over the first resist layer which has a second opening having a central portion emerging onto the first opening and a peripheral portion emerging onto the first layer; d) arranging a transparent plate in the second opening; and e) forming a third resist layer over the second resist layer and transparent plate which has a third opening emerging onto a central portion of the transparent plate.

    PACKAGE, FOR EXAMPLE AN OPTICAL PACKAGE, FOR AN INTEGRATED CIRCUIT
    8.
    发明公开
    PACKAGE, FOR EXAMPLE AN OPTICAL PACKAGE, FOR AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20230403791A1

    公开(公告)日：2023-12-14

    申请号：US18205655

    申请日：2023-06-05

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Romain COFFY ,  Younes BOUTALEB

    IPC: H05K1/03 ,  H05K1/11 ,  H05K1/02 ,  H05K3/46

    CPC classification number: H05K1/036 ,  H05K1/11 ,  H05K1/0209 ,  H05K3/4697 ,  H05K2201/10689 ,  H05K2201/10121

    Abstract: An integrated-circuit package includes a flexible electrical-connection element sandwiched between a first face of a first multilayer support substrate and a second face of a second multilayer support substrate. The flexible electrical-connection element laterally projects with respect to, and is in electrical contact with at least one of, the multilayer support substrates. The flexible electrical-connection element and the first multilayer support substrate include, at a first region, respectively two first mutually facing orifices defining together a first cavity. The first cavity is at least partially closed off by a first part of the second face of the second multilayer support substrate. A first component is located in the first cavity, attached at the first part of the second face of the second multilayer support substrate and in electrical contact with the flexible electrical-connection element through the second multilayer support substrate.

    INTEGRATED CIRCUIT OPTICAL PACKAGE
    9.
    发明申请
    INTEGRATED CIRCUIT OPTICAL PACKAGE 有权

    公开(公告)号：US20220392820A1

    公开(公告)日：2022-12-08

    申请号：US17833153

    申请日：2022-06-06

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Romain COFFY ,  Younes BOUTALEB

    IPC: H01L23/367 ,  H01L33/64 ,  H01L31/024 ,  H01L33/58 ,  H01L31/0232 ,  H01L33/62 ,  H01L31/02 ,  H01L23/00

    Abstract: A cap is mounted to a support substrate, the cap including a cap body and an optical shutter. The cap and support substrate define a housing. An electronic chip is disposed in the housing above the support substrate. A face of the electronic chip supports an optical device that is optically coupled with the optical shutter. The cap body is thermally conductive. Within the housing, a thermally conductive linking structure is coupled in a thermally conductive manner between the cap body and the electronic chip. The thermally conductive linking structure surrounds the electronic chip. A thermal interface material fills a portion of the housing between the thermally conductive linking structure and the cap body.

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