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公开(公告)号：US20080192873A1
公开(公告)日：2008-08-14
申请号：US12022725
申请日：2008-01-30
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
摘要翻译： 在一个实施例中，一种方法包括接收包括多个比特的数据信号。 该方法还包括产生时钟信号。 从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点 样品。 如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。 如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。
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公开(公告)号：US07256621B2
公开(公告)日：2007-08-14
申请号：US11089956
申请日：2005-03-25
申请人： Yolin Lih , William W. Walker
发明人： Yolin Lih , William W. Walker
IPC分类号： H03K19/20
CPC分类号： H03K19/0013 , H03K19/0963
摘要： Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation.
摘要翻译： 公开了用于电子电路的保持器电路，其选择性地将中间电路节点的电压电平维持在期望的水平。 在一个示例性实施例中，保持器晶体管或者从中间节点提供电流或漏极电流，以响应于这样做的信号来维持期望的电压电平。 保持器电路针对泄漏电流起作用，该泄漏电流从节点排出电流或将电流提供给节点。 电流设定晶体管与保持器晶体管串联耦合，以将通过保持器电路的最大电流设置为与该漏电流相关的值，优选地跟踪漏电流。 利用这种结构，电流设定晶体管能够跟踪由制造工艺的变化引起的漏电流的变化，从而提供动态泄漏补偿。
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公开(公告)号：US08138798B2
公开(公告)日：2012-03-20
申请号：US12511340
申请日：2009-07-29
CPC分类号： H03D13/008 , H03L7/085 , H03L7/089
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first input signal having a first phase; a second circuit input for receiving a second input signal having a second phase; a circuit output for outputting a circuit output signal; a first mixer cell comprising a first mixer cell input, a second mixer cell input, and a first mixer cell output; and a second mixer cell comprising a third mixer cell input, a fourth mixer cell input, and a second mixer cell output. The first circuit input is connected to the first and second mixer cell inputs, the second circuit input is connected to the second and fourth mixer cell inputs, and the first and second mixer cell outputs are combined to provide the circuit output. The current of the circuit output signal is proportional to a phase offset between the first and second phases.
摘要翻译： 在一个实施例中，电路包括用于接收具有第一相位的第一输入信号的第一电路输入端; 用于接收具有第二相位的第二输入信号的第二电路输入; 用于输出电路输出信号的电路输出; 第一混频器单元，包括第一混频器单元输入，第二混频器单元输入和第一混频器单元输出; 以及包括第三混频器单元输入，第四混频器单元输入和第二混频器单元输出的第二混频器单元。 第一电路输入连接到第一和第二混频器单元输入，第二电路输入连接到第二和第四混频器单元输入，并且组合第一和第二混频器单元输出以提供电路输出。 电路输出信号的电流与第一和第二相之间的相位偏移成比例。
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公开(公告)号：US20110310692A1
公开(公告)日：2011-12-22
申请号：US12819082
申请日：2010-06-18
申请人： Scott McLeod , William W. Walker
发明人： Scott McLeod , William W. Walker
IPC分类号： G11C8/04
摘要： In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array.
摘要翻译： 在一个实施例中，一种方法包括响应于在包括多个字的存储器阵列处的写入使能信号的断言，顺序地并且以第一时钟频率将数据从存储器阵列的开始处写入存储器阵列 直到内存数组已满。 该方法包括，与基于在存储器阵列处接收到的读取地址的数据相比，以与从存储器阵列读取数据的第一时钟频率相比慢的第二时钟频率异步地和以第二时钟频率写入数据。
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25.发明授权Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree 有权估计电路的时钟树中的抖动，并合成抖动感知和偏斜感知时钟树公开(公告)号：US07890904B2
公开(公告)日：2011-02-15
申请号：US11421988
申请日：2006-06-02
申请人： Rajeev Murgai , William W. Walker
发明人： Rajeev Murgai , William W. Walker
CPC分类号： G06F1/10 , G06F17/5045
摘要： In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The model includes a representation of each source of jitter in the circuit. The method also includes, to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining the jitter in each of the stages of the path or the pair of paths in the clock tree with each other.In one embodiment, to efficiently compute jitter and to achieve zero clock skew, a method synthesizes a symmetrical clock tree of a circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit approximate electrical equivalence to each other.
摘要翻译： 在一个实施例中，一种用于计算时钟树中的抖动的方法包括：将时钟树划分成多个级，并且根据与时钟树相关联的电路的至少一部分的模型计算一个或多个级中的抖动 。 该模型包括电路中每个抖动源的表示。 该方法还包括：计算与时钟树中的路径或一对路径相关联的抖动，将时钟树中的路径或路径对中的每个阶段中的抖动统一组合。 在一个实施例中，为了有效地计算抖动并实现零时钟偏移，一种方法合成电路的对称时钟树，其中从时钟树的根到时钟树的汇的所有路径中的相应阶段呈现近似的电等效 彼此。
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公开(公告)号：US20100049481A1
公开(公告)日：2010-02-25
申请号：US12197572
申请日：2008-08-25
IPC分类号： G06F17/10
CPC分类号： G06F1/10 , G06F17/5036 , G06F2217/62
摘要： A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.
摘要翻译： 描述了一种基于副本级构建时钟树的系统和方法。 系统和方法可以包括基于扇出来确定用于驱动输出缓冲器的负载电容的输入缓冲器的大小，基于输出缓冲器的大小，扇出和复制级确定线宽度和线长度 数学模型，以及将输出缓冲器和相应的输入缓冲器连接到在一个或多个预定金属层上布线并具有线长度和线宽度的导体。 导体放置在具有固定宽度的接地屏蔽内。
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公开(公告)号：US06693459B2
公开(公告)日：2004-02-17
申请号：US10045179
申请日：2002-01-11
IPC分类号： H03K19096
CPC分类号： H03K3/012 , H03K3/356139
摘要： The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.
摘要翻译： 本发明提供了一种技术，包括用于提高触发器中的速度的系统和方法，其具有耦合到评估级的预充电级。 在一个示例性实施例中，通过使用条件而不是无条件守门员来减少延迟，其中条件保持者仅在某些条件下具有保持者的功能。 在一些实施例中，在预充电阶段或评估阶段或两个阶段中存在条件保持器。 另一个实施例提供了评估阶段与一个或多个外部逻辑功能的组合。
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公开(公告)号：US08659973B2
公开(公告)日：2014-02-25
申请号：US12819082
申请日：2010-06-18
申请人： Scott McLeod , William W. Walker
发明人： Scott McLeod , William W. Walker
摘要： In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array.
摘要翻译： 在一个实施例中，一种方法包括响应于在包括多个字的存储器阵列处的写使能信号的断言，顺序地并且在第一时钟频率下将数据从存储器阵列的开始处开始写入存储器阵列 直到内存数组已满。 该方法包括，与基于在存储器阵列处接收到的读取地址的数据相比，以与从存储器阵列读取数据的第一时钟频率相比慢的第二时钟频率异步地和以第二时钟频率写入数据。
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29.发明授权Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture 有权边界增强滑动窗口方案（SWS），用于确定基于网格的时钟架构中的时钟时序公开(公告)号：US07788613B2
公开(公告)日：2010-08-31
申请号：US11428995
申请日：2006-07-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple original window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each original window location, expanding the original window location in one or more directions to generate a larger window location and generating a mesh simulation model including a detailed model inside the larger window location and an approximate model outside the larger window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.
摘要翻译： 在一个实施例中，一种方法包括访问包括多个顺序元素和时钟网格的芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的一组参数。 该方法还包括使用芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集合，确定覆盖时钟网格的多个原始窗口位置。 每个窗口位置包括芯片上的一个或多个顺序元件。 该方法还包括对于每个原始窗口位置，在一个或多个方向上扩展原始窗口位置以生成更大的窗口位置并生成包括较大窗口位置内的详细模型的网格模拟模型以及较大窗口外的近似模型 位置，模拟网格模拟模型，并基于网格模拟模型测量窗口位置中的顺序元素的时钟时序。 该方法还包括基于原始窗口位置中的顺序元素的测量时钟定时来收集关于芯片上的顺序元件的定时信息。
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30.发明授权Sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture 有权用于确定基于网格的时钟架构中的时钟定时的滑动窗口方案（SWS）公开(公告)号：US07725852B2
公开(公告)日：2010-05-25
申请号：US11428986
申请日：2006-07-06
申请人： Hongyu Chen , William W. Walker , Rajeev Murgai
发明人： Hongyu Chen , William W. Walker , Rajeev Murgai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62
摘要： In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each window location, generating a mesh simulation model including a detailed model inside the window location and an approximate model outside the window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the window locations.
摘要翻译： 在一个实施例中，一种方法包括访问包括多个顺序元素和时钟网格的芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的一组参数。 该方法还包括使用芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集，确定覆盖时钟网格的多个窗口位置。 每个窗口位置包括芯片上的一个或多个顺序元件。 该方法还包括对于每个窗口位置，生成包括窗口位置内的详细模型和窗口位置外的近似模型的网格模拟模型，模拟网格模拟模型，以及测量窗口位置中的顺序元素的时钟定时 基于网格模拟模型。 该方法还包括基于窗口位置中的顺序元素的测量时钟定时来收集关于芯片上的顺序元件的定时信息。
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