公开(公告)号：US20140218347A1

公开(公告)日：2014-08-07

申请号：US14167868

申请日：2014-01-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHEOL-GON LEE ,  Chong Chul Chai ,  Joon-Chul Goh ,  Yeong-Keun Kwon ,  Jong Hee Kim

IPC: G02F1/1362 ,  G09G3/36

CPC classification number: G02F1/136286 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2320/028

Abstract: In a liquid crystal display one pixel is divided into two subpixels, the two subpixels are connected to two subdata lines extending from one data line, and a desired data voltage is applied by using a data driving switching element connected to the subdata line, thereby reducing the number of data lines needed to reduce the cost of the driver and preventing a lack of space to mount the data driver while dividing one pixel into two subpixels and differently applying voltages of the two subpixels.

Abstract translation: 在液晶显示器中，一个像素被分成两个子像素，两个子像素连接到从一个数据线延伸的两个子数据线，并且通过使用连接到子数据线的数据驱动开关元件来施加期望的数据电压，从而减少 减少驱动器成本所需的数据线数量，并且防止在将一个像素分成两个子像素并且不同地施加两个子像素的电压时安装数据驱动器的空间不足。

公开(公告)号：US11776482B2

公开(公告)日：2023-10-03

申请号：US17699943

申请日：2022-03-21

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Soo Yeon Lee

IPC: G09G3/32 ,  G09G3/3266 ,  G09G3/36

CPC classification number: G09G3/3266 ,  G09G3/3677 ,  G09G2310/08

Abstract: A scan driver for a display device includes a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage includes: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.

公开(公告)号：US11551588B2

公开(公告)日：2023-01-10

申请号：US17194872

申请日：2021-03-08

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Il-Joo Kim ,  Sang-Uk Lim

IPC: G09F9/33 ,  G09G3/32 ,  H01L25/075 ,  G09G3/20

Abstract: A display device includes: a first pixel including a first light emitting diode (LED) and a first capacitor including a first electrode connected to a first power source voltage providing a driving voltage to an anode of the first light emitting diode (LED) or to an initialization voltage, and a second electrode connected to the anode of the first light emitting diode (LED); and a second pixel including a second light emitting diode (LED) and a second capacitor including a first electrode connected to the first power source voltage providing the driving voltage to an anode of the second light emitting diode (LED) or to an initialization voltage, and a second electrode connected to the anode of the second light emitting diode (LED), wherein capacitance of the second capacitor is less than capacitance of the first capacitor.

公开(公告)号：US10991300B2

公开(公告)日：2021-04-27

申请号：US16134923

申请日：2018-09-18

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Ji Hye Lee

IPC: G09G3/3208 ,  G09G3/3233 ,  G09G3/3266

Abstract: A pixel includes an organic light-emitting diode (OLED), a storage capacitor, and first to fourth transistors. The first transistor includes a gate electrode (GE), a first electrode (FE), and a second electrode (SE), and is configured to control, in response to a voltage of a first node (FN) coupled to the GE, current supplied from a first power source (PS) coupled to the FE to a second PS via the OLED. The storage capacitor is coupled between the FN and the first PS. The second transistor is coupled between a data line and the first transistor. The third transistor includes a FE coupled to the FN and a SE coupled to the SE of the first transistor. The fourth transistor includes a FE coupled to the FN and a SE coupled to the SE of the first transistor, and is configured to transmit an initialization voltage to the FN.

公开(公告)号：US10078995B2

公开(公告)日：2018-09-18

申请号：US15084022

申请日：2016-03-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jong Hee Kim ,  Ji Sun Kim ,  Young Wan Seo ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G5/00 ,  H03K17/687 ,  G09G3/3266 ,  G09G3/36

CPC classification number: G09G5/00 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08

Abstract: A gate driver includes a plurality of stage circuits to output a clock signal from the outside as gate signals. A jth stage circuit includes an input unit to charge a first node at an initial voltage when a first input signal is input to a first input terminal, a buffer unit to output the clock signal as a gate signal to an output terminal when the initial voltage is supplied to the first node, a holding unit to maintain the first node at a reset power source level when the clock signal is supplied to the holding unit, and an inverter unit to supply the clock signal or the reset power source to the holding unit. The input unit maintains the first node at a second input signal input voltage to a second input terminal when a third input signal is input to a third input terminal.

公开(公告)号：US09870730B2

公开(公告)日：2018-01-16

申请号：US14920596

申请日：2015-10-22

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Ji-Sun Kim ,  Jun Hyun Park ,  Young Wan Seo ,  Jae Keun Lim ,  Chong Chul Chai

IPC: G09G3/36 ,  G09G3/20 ,  H03K19/0175

CPC classification number: G09G3/2092 ,  G09G2310/0286 ,  H03K19/017509

Abstract: A gate circuit according to an exemplary embodiment of the present inventive concept comprises a plurality of stages, each receiving a clock signal and outputting a gate signal and a carry signal. One of the plurality of stages includes a first transistor of which a first terminal and a control terminal are connected to each other and a carry signal of a stage before previous stage is input to the first terminal and the control terminal and a second transistor of which a gate signal of the previous stage is input to a first terminal, a control terminal is connected with a second terminal of the first transistor, and an output terminal is connected to a first node.

公开(公告)号：US12022692B2

公开(公告)日：2024-06-25

申请号：US17472088

申请日：2021-09-10

Applicant: Samsung Display Co., Ltd.

Inventor： Doo-Young Lee ,  Jong Hee Kim ,  Yoo Mi Ra ,  Kyung-Ho Park ,  Geun Ho Lee ,  Chang-Soo Lee ,  Tak-Young Lee ,  Bo Yong Chung ,  Jung Hwan Hwang

IPC: H01L29/08 ,  H10K59/121 ,  H10K59/131

CPC classification number: H10K59/1216 ,  H10K59/1213 ,  H10K59/131

Abstract: A light emitting display device including: a first pixel including a first lower storage electrode, a first gate electrode of a first driving transistor, and a first upper storage electrode; and a second pixel provided near the first pixel, and including a second lower storage electrode, a second gate electrode of a second driving transistor, and a second upper storage electrode. In a plan view, the first gate electrode and the second gate electrode have first sides facing each other, the first side of the first gate electrode is positioned inside a border of the first lower storage electrode or the first upper storage electrode in a plan view, and the first side of the second gate electrode is positioned inside a border of the second lower storage electrode or the second upper storage electrode in a plan view.

公开(公告)号：US11699399B2

公开(公告)日：2023-07-11

申请号：US17577301

申请日：2022-01-17

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Tak Young Lee ,  Bo Yong Chung ,  Yang Hwa Choi

IPC: G09G3/3266 ,  G09G3/3258

CPC classification number: G09G3/3266 ,  G09G3/3258 ,  G09G2310/0202

Abstract: A scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes first-to-sixth transistors and a first capacitor. The first transistor is connected to a first Q node, a first scan clock line, and a first scan line. A second transistor is connected to a first scan carry line and the first Q node. A third transistor is connected to a first sensing carry line and a second sensing carry line. A fourth transistor is connected to a first control line and the third transistor. A fifth transistor is connected to the fourth transistor, a second control line, and a first node. A first capacitor is connected to the fifth transistor. A sixth transistor is connected to a third control line, the first node, and the first Q node.

公开(公告)号：US11282463B2

公开(公告)日：2022-03-22

申请号：US16744009

申请日：2020-01-15

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Soo Yeon Lee

IPC: G09G3/32 ,  G09G3/3266 ,  G09G3/36

Abstract: A scan driver for a display device includes a plurality of scan stage groups, each of the scan stage groups including a first scan stage and a second scan stage. The first scan stage includes: a first transistor including a gate electrode coupled to a first Q node, one electrode coupled to a first scan clock line, and another electrode coupled to a first scan line; a second transistor including a gate electrode and one electrode, which are coupled to a first scan carry line, and another electrode coupled to the first Q node; a third transistor including a gate electrode coupled to a first control line and one electrode coupled to a first sensing carry line; a fourth transistor including a gate electrode coupled to the other electrode of the third transistor, one electrode coupled to a second control line, and another electrode coupled to a first node; a first capacitor including one electrode coupled to the one electrode of the fourth transistor and another electrode coupled to the gate electrode of the fourth transistor; a fifth transistor including a gate electrode coupled to a third control line, one electrode coupled to the first node, and another electrode coupled to the first Q node; and a sixth transistor including a gate electrode coupled to the first Q node, one electrode coupled to the second control line, and another electrode coupled to the first node.

公开(公告)号：US11120750B2

公开(公告)日：2021-09-14

申请号：US16912633

申请日：2020-06-25

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim

IPC: G09G3/3291 ,  G09G3/3258

Abstract: The disclosure relates to a stage and a scan driver including the stage. The stage is connected to each of scan lines and supplies a scan signal and a sensing signal to the scan lines. The stage includes an input unit configured to control voltages of a first node and a second node based on a first control signal and a previous stage carry signal, and an output buffer including an eleventh node and a twelfth node electrically connected to the first node and the second node, respectively, in response to a second control signal, and configured to output a carry signal and the scan signal in response to a scan clock signal according to voltages of the eleventh node and the twelfth node and to output the sensing signal in response to a sensing clock signal.