Abstract:
A pixel includes a light emitting element, a first transistor connected between first and second nodes and that generates a driving current flowing from a first power line to a second power line through the light emitting element, a second transistor connected between a data line and the first node and turned on in response to a fourth scan signal, a third transistor connected between the second node and a third node corresponding to a gate electrode of the first transistor and turned on in response to a second scan signal, a fourth transistor connected between the third node and a third power line providing a third power voltage and turned on in response to a first scan signal, and a fifth transistor connected between the first and fourth nodes and turned on in response to a fifth scan signal.
Abstract:
There are provided a gate driver and a display device including the same. The gate driver includes: a first scan driver; a first sensing driver; a first scan clock line; and a first sensing clock line. The first scan clock line includes a first scan clock main line extending in one direction, and a first scan clock connection line connected to the first scan clock main line and the first scan driver. The first sensing clock line includes a first sensing clock main line extending in one direction, and a first sensing clock connection line connected to the first sensing clock main line and the first sensing driver. The first scan clock main line is closer to each of the first scan driver and the first sensing driver than the first sensing clock main line.
Abstract:
An organic light emitting diode display including: a data wiring that includes a main data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wiring that includes a main driving voltage line disposed in the display area and a first driving voltage line that is connected with the main driving voltage line and disposed in the peripheral area while extending in a first direction; and a driving low-voltage wiring that includes a cathode extending to the peripheral area while overlapping the display area, and a plurality of first driving low-voltage connection portions that are connected with the cathode and disposed in the peripheral area, wherein each of the plurality of first driving low-voltage connection portions comprises a wiring portion extended in the first direction and a pad portion electrically connected with the wiring portion.
Abstract:
A display device includes a display panel including a plurality of pixels, a timing controller which generates an emission start signal, an emission driver which supplies an emission control signal to the plurality of pixels based on the emission start signal received from the timing controller, a first scan driver which supplies a first scan signal to the plurality of pixels, a second scan driver which supplies a second scan signal to the plurality of pixels, and a data driver which supplies a data signal to the plurality of pixels. The timing controller adjusts a period in which the emission start signal is supplied based on a change of a driving frequency.
Abstract:
A pixel including a light emitter; a first transistor including first and second electrodes respectively connected to power and the light emitter, the first transistor controlling, driving current a first capacitor between a second and third node; a second transistor between the third node and data line and turned on by a scan signal; a third transistor between a first and second node, and turned on by a control signal; a fourth transistor between power and the third node, and turned on by a emission control signal; a fifth transistor between power and the first electrode, and turned on by the emission control signal; a sixth transistor between the second node and the light emitter, and turned on by another emission control signal; and a second capacitor between power and the first node, wherein the fourth, fifth and sixth transistors turn-on/off at least four times in a non-emission period.
Abstract:
A display device includes: an initialization power line extending along a first direction; a scan line extending along the first direction and spaced apart from the initialization power line, a data line and a driving voltage line insulated from the initialization power line and the scan line and extending along the second direction; a first switching element including a first electrode connected to the driving voltage line, a first gate electrode overlapping the initialization power line, and a second electrode; a second switching element including a third electrode connected to the first gate electrode, a second gate electrode connected to the scan line, and a fourth electrode; a third switching element including a fifth electrode connected to the fourth electrode, a third gate electrode connected to the initialization power line, and a sixth electrode connected to the second electrode; and a light emitting element connected to the second electrode.
Abstract:
A pixel including an organic light emitting diode; a first transistor for controlling the amount of current flowing from a first driving power source to a second driving power source via the organic light emitting diode, corresponding to a voltage of a first node; a second transistor coupled between the first node and a second node, the second transistor being turned on when a scan signal is supplied to an ith (i is a natural number) scan line; a third transistor coupled between the second node and an anode electrode of the organic light emitting diode; a first capacitor coupled between a data line and the second node; and a fourth transistor coupled between an initialization power source and the anode electrode of the organic light emitting diode. The fourth transistor is turned on in response to a first control signal being supplied to a first control line.
Abstract:
A stage includes first, second, and third outputs and first and second signal processors. The first output supplies a scan signal to a first output terminal based on signals to first and second input terminals and the voltage of a first node. The second output is connected to a first power source and supplies an emission control signal to a second output terminal based on signals to the first input terminal, the first output terminal, and a third input terminal. The third output is connected to the first power source and supplies an inverted emission control signal to a third output terminal based on signals to the first input terminal and second output terminal. The first signal processor controls the first node voltage based on a signal to a fourth input terminal. The second signal processor controls the first node voltage based on the signal to the second input terminal.
Abstract:
In a scan driver including a plurality of stages configured to supply scan signals to scan lines, the scan driver includes: an i−1th stage configured to supply an i−1th scan signal to an i−1th scan line while controlling a node Qi−1 (i is a natural number) in response to a first clock signal, a third clock signal, and a control voltage; an ith stage configured to supply an ith scan signal to an ith scan line while controlling a node Qi in response to a second clock signal, a fourth clock signal, and the control voltage; and a controller connected to the i−1th stage and the ith stage, and configured to supply the control voltage.
Abstract:
Disclosed herein is a thin film transistor array panel, including: an insulating substrate; a gate electrode formed on the insulating substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer; a source electrode and a drain electrode formed on the semiconductor layer and the gate insulating layer and facing each other; and a pixel electrode connected to the drain electrode and applied with a voltage from the drain electrode, wherein a thickness of the gate insulating layer which overlaps the drain electrode but does not overlap the semiconductor layer is formed to be thinner than that which overlaps the semiconductor.