公开(公告)号：US20240204060A1

公开(公告)日：2024-06-20

申请号：US18065660

申请日：2022-12-14

申请人： Intel Corporation

发明人： Rohit Galatage ,  Cheng-Ying Huang ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Jami Wiedemer ,  Munzarin Qayyum ,  Evan Clinton

IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/775 ,  H01L2029/42388

摘要： IC structures with nanoribbon stacks without dielectric protection caps for top nanoribbons, and associated methods and devices, are disclosed. An example IC structure includes a stack of nanoribbons, an opening over the top nanoribbon of the stack of nanoribbons, and a gate electrode material in the opening, where the opening has a first portion, a second portion, and a third portion, the second portion is between the first portion and the third portion, and where a width of a portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the first portion. In such an IC structure, a gate insulator on the sidewalls of the first portion of the opening is materially discontinuous from a gate insulator on the sidewalls of the third portion of the opening.

公开(公告)号：US12010871B2

公开(公告)日：2024-06-11

申请号：US17199991

申请日：2021-03-12

申请人： Japan Display Inc.

发明人： Masashi Tsubuku ,  Tatsuya Toda

IPC分类号： H10K59/121 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： H10K59/1213 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78648 ,  H01L29/7869 ,  H01L27/1225 ,  H01L2029/42388

摘要： A thin film transistor including: an active layer formed of an oxide semiconductor including at least indium and gallium; a gate electrode; a first gate insulating layer disposed between the active layer and the gate electrode on the gate electrode side; and a second gate insulating layer, which is a hydrogen block layer, disposed between the active layer and the gate electrode on the active layer side.

公开(公告)号：US11871617B2

公开(公告)日：2024-01-09

申请号：US18078072

申请日：2022-12-08

申请人： Samsung Display Co., LTD.

发明人： Keun Woo Kim ,  Tae Wook Kang ,  Han Bit Kim ,  Bum Mo Sung ,  Do Kyeong Lee ,  Jae Seob Lee

IPC分类号： H01L27/32 ,  H10K59/121 ,  H01L29/66 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H10K59/12

CPC分类号： H10K59/1213 ,  H10K59/1216 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02661 ,  H01L21/02675 ,  H01L27/1222 ,  H01L27/1255 ,  H01L27/1274 ,  H01L29/42384 ,  H01L29/6675 ,  H01L29/78645 ,  H01L29/78672 ,  H01L29/78696 ,  H01L2029/42388 ,  H10K59/1201

摘要： A light emitting display device includes: a light emitting element; a second transistor connected to a scan line; a first transistor which applies a current to the light emitting element; a capacitor connected to a gate electrode of the first transistor; and a third transistor connected to an output electrode of the first transistor and the gate electrode of the first transistor. Channels of the second transistor, the first transistor, and the third transistor are disposed in a polycrystalline semiconductor layer, and a width of a channel of the third transistor is in a range of about 1 μm to about 2 μm, and a length of the channel of the third transistor is in a range of about 1 μm to about 2.5 μm.

公开(公告)号：US20190237582A1

公开(公告)日：2019-08-01

申请号：US16326575

申请日：2017-08-18

申请人： Rutgers, The State University of New Jersey

发明人： Yicheng Lu ,  Wen-Chiang Hong ,  Chieh-Jen Ku ,  Kuang Sheng ,  Rui Li

IPC分类号： H01L29/786 ,  H01L21/02 ,  C23C16/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423

CPC分类号： H01L29/7869 ,  C23C16/40 ,  C23C16/403 ,  C23C16/407 ,  H01L21/02554 ,  H01L21/0262 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7391 ,  H01L2029/42388

摘要： Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.

公开(公告)号：US20180294160A1

公开(公告)日：2018-10-11

申请号：US16008256

申请日：2018-06-14

申请人： Sakai Display Products Corporation

发明人： Ryo MURATA

IPC分类号： H01L21/28 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L21/28247 ,  H01L21/28008 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78606 ,  H01L29/78696 ,  H01L2029/42388

摘要： There is provided a TFT substrate that prevents corrosion of a gate electrode and a method for manufacturing the TFT substrate. The TFT substrate comprises a substrate; a gate comprising a gate electrode and a gate wiring, the gate comprising copper and formed on one surface of the substrate; a protection film to cover the gate; an insulation film formed on the protection film; a semiconductor film formed on the insulation film; and a source and a drain formed on the semiconductor film and facing each other with a space therebetween above the gate electrode, wherein the protection film covers entire exposed surface of the gate.

公开(公告)号：US20180190827A1

公开(公告)日：2018-07-05

申请号：US15908215

申请日：2018-02-28

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yutaka OKAZAKI ,  Daisuke MATSUBAYASHI ,  Yuichi SATO

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/441 ,  H01L29/45 ,  H01L29/423 ,  H01L27/12

CPC分类号： H01L29/7869 ,  H01L21/441 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7853 ,  H01L29/78603 ,  H01L29/78696 ,  H01L2029/42388

摘要： A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating layer and an oxide semiconductor layer are deposited over the first insulating layer. A second oxide insulating layer is deposited over the oxide semiconductor layer and the first insulating layer. A second insulating layer and a first conductive layer are deposited over the second oxide insulating layer. A gate electrode layer, a gate insulating layer, and a third oxide insulating layer are formed by etching. A sidewall insulating layer including a region in contact with a side surface of the gate electrode layer is formed. A second conductive layer is deposited over the gate electrode layer, the sidewall insulating layer, the oxide semiconductor layer, and the first insulating layer. A third conductive layer is deposited over the second conductive layer. A low-resistance region is formed in the oxide semiconductor layer by performing heat treatment. An element contained in the second conductive layer moves from the second conductive layer to the oxide semiconductor layer side by performing the heat treatment. An element contained in the oxide semiconductor layer moves from the oxide semiconductor layer to the third conductive layer side by performing the heat treatment.

公开(公告)号：US10014390B1

公开(公告)日：2018-07-03

申请号：US15729105

申请日：2017-10-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Guillaume Bouche ,  Julien Frougier ,  Ruilong Xie

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308 ,  H01L29/423

CPC分类号： H01L29/66553 ,  B82Y10/00 ,  H01L21/3086 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696 ,  H01L2029/42388

摘要： Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a first nanosheet channel layer, a second nanosheet channel layer, and first, second, and third sacrificial layers that are vertically arranged between the first and second nanosheet channel layers. The first, second, and third sacrificial layers are laterally recessed relative to the first and second nanosheet channel layers to form a cavity indented into a sidewall of the first body feature. The second sacrificial layer is laterally recessed to a lesser extent than the first sacrificial layer or the third sacrificial layer such that an end of the second sacrificial layer projects into the cavity between the first and third sacrificial layers. A dielectric spacer is formed in the first and second portions of cavity between the first and second nanosheet channel layers.

公开(公告)号：US10014180B1

公开(公告)日：2018-07-03

申请号：US15681654

申请日：2017-08-21

申请人： GLOBALFOUNDRIES Inc.

发明人： Neal A. Makela ,  Vimal K. Kamineni ,  Pei Liu ,  Chih-Chiang Chang

IPC分类号： H01L21/285 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/423

CPC分类号： H01L21/28568 ,  H01L21/0217 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/31055 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66568 ,  H01L2029/42388

摘要： A structure and method for forming a tungsten region for a replacement metal gate (RMG). The method for forming the tungsten region may include, among other things, forming a first tungsten region i.e., tungsten seed layer, on a liner in a trench of a dielectric layer; removing a portion of the liner and the tungsten seed layer to expose an uppermost surface of a work function metal (WFM) layer wherein an uppermost surface of the liner and tungsten seed layer is positioned below an uppermost surface of the dielectric layer; and forming a second tungsten region from the tungsten seed layer. The tungsten region may be formed to contact the uppermost surface liner, the uppermost surface of WFM layer, and/or the sidewalls of the trench. The tungsten region may include a single crystallographic orientation. The tungsten region may also include an uppermost surface with a substantially arcuate cross-sectional geometry.

公开(公告)号：US20180166550A1

公开(公告)日：2018-06-14

申请号：US15485188

申请日：2017-04-11

申请人： Samsung Electronics Co., Ltd.

发明人： Mark S. Rodder ,  Borna J. Obradovic

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/42392 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785 ,  H01L2029/42388

摘要： A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.

公开(公告)号：US20180138091A1

公开(公告)日：2018-05-17

申请号：US15869761

申请日：2018-01-12

申请人： International Business Machines Corporation

发明人： Hari V. Mallela ,  Reinaldo A. Vega ,  Rajasekhar Venigalla

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/265 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L21/82385 ,  H01L21/02263 ,  H01L21/26566 ,  H01L21/32 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2029/42388

摘要： A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.