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    NODE AND METHOD FOR GENERATING SHORTENED NAME ROBUST AGAINST CHANGE IN HIERARCHICAL NAME IN CONTENT-CENTRIC NETWORK (CCN)
    21.
    发明申请
    NODE AND METHOD FOR GENERATING SHORTENED NAME ROBUST AGAINST CHANGE IN HIERARCHICAL NAME IN CONTENT-CENTRIC NETWORK (CCN) 有权
    用于生成内容中心网络（CCN）中分层名称变化的缓冲名称的节点和方法

    公开(公告)号：US20130282854A1

    公开(公告)日：2013-10-24

    申请号：US13860971

    申请日：2013-04-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myeong Wuk JANG ,  Jae Hoon KIM ,  Do Jun BYUN

    IPC: H04L29/08 ,  G06F15/167

    CPC classification number: H04L67/10 ,  G06F15/167 ,  H04L61/303 ,  H04L67/2842 ,  H04L67/327

    Abstract: A node and a method for generating a shortened name robust against a change in a hierarchical name in a Content-Centric Network (CCN) are provided. The method includes receiving a packet requesting content including a hierarchical name of the content, and determining whether a prefix of the hierarchical name is identical to a name of the node. The method further includes generating a shortened name by removing the prefix from the hierarchical name if the prefix is identical to the name component, and changing the hierarchical name to the shortened name. The shortened name is used to check whether the corresponding content is stored in the content cache, to check whether the same content-request packet is already under processing, and to decide an outgoing face to which the content-request packet is transmitted.

    Abstract translation: 提供了一种用于生成针对以内容为中心的网络（CCN）中的分层名称的变化而鲁棒的缩写名称的节点和方法。 该方法包括接收包含内容的层次名称的请求内容的分组，以及确定分层名称的前缀是否与该节点的名称相同。 该方法还包括：如果该前缀与该名称组件相同，并且将该层次名称改变为缩写名称，则通过从该层级名称中移除该前缀来生成缩写名称。 缩短的名称用于检查对应的内容是否存储在内容缓存中，以检查相同的内容请求分组是否已在处理中，并且确定发送内容请求分组的出局面。

    MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    23.
    发明公开
    MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240260477A1

    公开(公告)日：2024-08-01

    申请号：US18364619

    申请日：2023-08-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Hoon KIM ,  Hyeonwoo SEO ,  YoungJun CHO

    IPC: H10N50/01 ,  H10B61/00 ,  H10N50/10

    CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10

    Abstract: A method of manufacturing a magnetic memory device may include forming a bottom electrode layer on a substrate; forming a block structure on the bottom electrode layer; performing a first deposition process on the bottom electrode layer to form a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer on the bottom electrode layer; performing a second deposition process on the free magnetic layer to form a capping layer on the free magnetic layer; and performing an etching process after forming a hard mask on the capping layer to form magnetic tunnel junction patterns. The first deposition process may include irradiating a first beam toward the substrate. The second deposition process may include irradiating a second beam toward the substrate. The second beam may have a greater angle than the first beam with respect to a normal line perpendicular to an upper surface of the substrate.

    VARIABLE RESISTANCE MEMORY DEVICE
    24.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE 有权

    公开(公告)号：US20220102427A1

    公开(公告)日：2022-03-31

    申请号：US17230029

    申请日：2021-04-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae Hoon KIM ,  Sang Hwan PARK ,  Yong-Sung PARK ,  Hyeonwoo SEO ,  Se Chung OH ,  Hyun CHO

    IPC: H01L27/22 ,  H01L27/24

    Abstract: A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    25.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20210183862A1

    公开(公告)日：2021-06-17

    申请号：US17038355

    申请日：2020-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong-hoon SON ,  Jae Hoon KIM ,  Kwang-Ho PARK ,  Seungjae JUNG

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L29/66

    Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

    INTERNET-OF-THINGS MODULE
    26.
    发明申请
    INTERNET-OF-THINGS MODULE 审中-公开

    公开(公告)号：US20190087581A1

    公开(公告)日：2019-03-21

    申请号：US16037554

    申请日：2018-07-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae Hoon KIM ,  Bo Gyeong KANG

    IPC: G06F21/57 ,  G06F21/78 ,  G06F12/14 ,  G06F8/71 ,  G06F8/65 ,  H04L9/08

    Abstract: An Internet of Things module includes a memory including a boot area for storing boot firmware and first security information and a security area for storing a firmware release version and second security information, and a processor to perform a boot process of the Internet of Things module using the boot firmware in the boot area and to determine whether the boot process of the Internet of Things module is progressed or stopped through comparing the first security information in the boot area with the second security information in the security area and through comparing a version of the boot firmware in the boot area with the firmware release version in the security area.

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