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    Semiconductor device including blocking pattern, electronic system, and method of forming the same
    24.
    发明授权
    Semiconductor device including blocking pattern, electronic system, and method of forming the same 有权

    公开(公告)号：US12082423B2

    公开(公告)日：2024-09-03

    申请号：US17679863

    申请日：2022-02-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunmook Choi ,  Jooheon Kang ,  Sanghoon Kim ,  Jihong Kim

    IPC: H10B63/00

    CPC classification number: H10B63/34

    Abstract: A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.

    IMAGE SENSOR INCLUDING STACKED CHIPS
    26.
    发明公开
    IMAGE SENSOR INCLUDING STACKED CHIPS 审中-公开

    公开(公告)号：US20230197756A1

    公开(公告)日：2023-06-22

    申请号：US18065531

    申请日：2022-12-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeongjin Lee ,  Jeongsoon Kang ,  Jihong Kim ,  Changyong Um

    IPC: H01L27/146

    CPC classification number: H01L27/14634 ,  H01L27/1463 ,  H01L27/14621 ,  H01L27/14636 ,  H01L27/14645

    Abstract: An image sensor includes a first lower chip, and an upper chip on and bonded to the first lower chip. The first lower chip and the upper chip collectively provide a plurality of pixels. A respective pixel of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, and a transfer gate in the upper chip, and a plurality of lower transistors in the first lower chip. A first lower transistor among the plurality of lower transistors includes a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers.

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