公开(公告)号：US09991203B2

公开(公告)日：2018-06-05

申请号：US15298855

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Jong-Min Baek ,  Nae-In Lee ,  Eun-Ji Jung

IPC: H01L29/40 ,  H01L21/44 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.

公开(公告)号：US09773699B2

公开(公告)日：2017-09-26

申请号：US15000302

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

公开(公告)号：USD794887S1

公开(公告)日：2017-08-15

申请号：US29549227

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Designer： Jin-Nam Kim ,  Ji-Yeun Yoon ,  Dong-Won Chun

公开(公告)号：USD794886S1

公开(公告)日：2017-08-15

申请号：US29549222

申请日：2015-12-21

Applicant: Samsung Electronics Co., Ltd.

Designer： Jin-Nam Kim ,  Ji-Yeun Yoon ,  Dong-Won Chun

公开(公告)号：USD789631S1

公开(公告)日：2017-06-13

申请号：US29548198

申请日：2015-12-11

Applicant: Samsung Electronics Co., Ltd.

Designer： Jin-Nam Kim ,  Ji-Yeun Yoon ,  Dong-Won Chun

公开(公告)号：USD788391S1

公开(公告)日：2017-05-30

申请号：US29549409

申请日：2015-12-22

Applicant: Samsung Electronics Co., Ltd.

Designer： Jin-Nam Kim ,  Ji-Yeun Yoon ,  Dong-Won Chun