Nonlinear self-interference cancellation with sampling rate mismatch

    公开(公告)号:US10797739B1

    公开(公告)日:2020-10-06

    申请号:US16440626

    申请日:2019-06-13

    Abstract: A method for providing nonlinear self-interference cancellation of a wireless communication device includes: receiving digital samples of an interfering signal having a first sampling rate and a corrupted victim signal having a second sampling rate; generating a kernel vector based on the interfering signal, wherein the kernel vector has terms of nonlinear self-interference; estimating the nonlinear self-interference of the corrupted victim signal using the terms of the nonlinear self-interference; and providing an estimation of a desired signal by cancelling the nonlinear self-interference from the corrupted victim signal.

    NONLINEAR SELF-INTERFERENCE CANCELLATION WITH SAMPLING RATE MISMATCH

    公开(公告)号:US20200295793A1

    公开(公告)日:2020-09-17

    申请号:US16440626

    申请日:2019-06-13

    Abstract: A method for providing nonlinear self-interference cancellation of a wireless communication device includes: receiving digital samples of an interfering signal having a first sampling rate and a corrupted victim signal having a second sampling rate; generating a kernel vector based on the interfering signal, wherein the kernel vector has terms of nonlinear self-interference; estimating the nonlinear self-interference of the corrupted victim signal using the terms of the nonlinear self-interference; and providing an estimation of a desired signal by cancelling the nonlinear self-interference from the corrupted victim signal.

    Time-domain IQ mismatch compensator with frequency-domain observations

    公开(公告)号:US10749555B2

    公开(公告)日:2020-08-18

    申请号:US16243710

    申请日:2019-01-09

    Abstract: A system, method, and electronic device for compensating in-phase (I) and quadrature (Q) mismatch (IQMM) are herein disclosed. The system includes an IQ mismatch compensator (IQMC) configured to compensate for IQMM between a time-domain I signal and a time-domain Q signal using filter weight coefficients, and output a compensated I signal and a compensated Q signal, a fast Fourier transformation (FFT) circuit configured to perform an FFT on the compensated I signal and the compensated Q signal to a frequency-domain compensated signal, and a coefficient updater configured to update the filter weight coefficients based on a frequency-domain observation of the frequency-domain compensated signal.

    SYSTEM AND METHOD FOR PROVIDING FILTER/MIXER STRUCTURE FOR OFDM SIGNAL SEPARATION

    公开(公告)号:US20190140877A1

    公开(公告)日:2019-05-09

    申请号:US15890952

    申请日:2018-02-07

    Abstract: Apparatuses and methods of manufacturing same, systems, and methods to separate out a target numerology from a mixed numerology signal are described. In one aspect, a three mixer, two filter (3M2F) structure can separate out any one of multiple possible target numerologies. In another aspect, a sampled signal is frequency rotated such that one end of the target numerology is within one end of a passband of a first filter and a second filter, filtered by the first filter which attenuates any signal past the one end of the passband, frequency rotated again such that the opposite end of the target numerology is within the opposite end of the passband, filtered by the second filter which attenuates any signal past the opposite end of the passband, and frequency rotated a third time such that the target numerology returns to its original location in the frequency domain in the sampled signal.

    EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR

    公开(公告)号:US20180254785A1

    公开(公告)日:2018-09-06

    申请号:US15974218

    申请日:2018-05-08

    CPC classification number: H04B1/0042 H04B1/0046 H04B3/462

    Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.

Patent Agency Ranking