公开(公告)号：US10950628B2

公开(公告)日：2021-03-16

申请号：US16869581

申请日：2020-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L29/10 ,  H01L23/48 ,  H01L27/11568 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11565

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

公开(公告)号：US10833093B2

公开(公告)日：2020-11-10

申请号：US16217219

申请日：2018-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Cheon Baek

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11568

Abstract: A semiconductor device includes a substrate having first and second regions, gate electrodes stacked in a first direction perpendicular to the substrate in the first region, and extending by different lengths in a second direction perpendicular to the first direction in the second region, first separation regions in the first and second regions through the gate electrodes, extending in the second direction, and spaced apart from each other in a third direction perpendicular to the first and second directions, second separation regions between the first separation regions through the gate electrodes and extending in the second direction, portions of the second separation regions being spaced apart from each other in the second direction in the second region, and an insulation region extending in the third direction to separate at least one of the gate electrodes into portions adjacent to each other in the second direction.

公开(公告)号：US10685975B2

公开(公告)日：2020-06-16

申请号：US16174187

申请日：2018-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek

IPC: H01L27/115 ,  H01L21/768 ,  H01L29/10 ,  H01L23/48 ,  H01L23/52 ,  H01L21/02 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/11565

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

公开(公告)号：US10573657B2

公开(公告)日：2020-02-25

申请号：US16206035

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Cheon Baek ,  Geun Won Lim

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11573 ,  H01L23/535 ,  H01L27/11582 ,  H01L21/28

Abstract: A method for fabricating a non-volatile memory device is provided. The method includes forming a channel hole and a first contact hole simultaneously, several times, in order to achieve a desired a high aspect ratio.