中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.018 seconds)

    Semiconductor device including multi-stack structure
    2.
    发明授权
    Semiconductor device including multi-stack structure 有权

    公开(公告)号：US11056502B2

    公开(公告)日：2021-07-06

    申请号：US16365827

    申请日：2019-03-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Cheon Baek

    IPC: H01L23/538 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/11568 ,  H01L27/11575

    Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.

    Semiconductor device including a through wiring area
    3.
    发明授权
    Semiconductor device including a through wiring area 有权

    公开(公告)号：US10971432B2

    公开(公告)日：2021-04-06

    申请号：US16388370

    申请日：2019-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seok Cheon Baek

    IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11556

    Abstract: A semiconductor device includes a peripheral circuit area disposed on a first substrate and including circuit devices. A memory cell area is disposed on a second substrate and includes memory cells. A through wiring area includes a through contact plug and an insulating area. The through contact plug extends through the memory cell area and the second substrate and connects the memory cell area to the circuit devices. The insulating area surrounds the through contact plug. The insulating area includes a first insulating layer penetrating through the second substrate, a plurality of second insulating layers, a third insulating layer having a vertical extension portion, and a plurality of horizontal extension portions extended in parallel to a top surface of the second substrate from a side surface of the vertical extension portion to contact the second insulating layers.

    Semiconductor devices including channel structures
    4.
    发明授权
    Semiconductor devices including channel structures 有权

    公开(公告)号：US10930664B2

    公开(公告)日：2021-02-23

    申请号：US16454293

    申请日：2019-06-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoon Hwan Son ,  Seok Cheon Baek ,  Ji Sung Cheon

    IPC: H01L27/115 ,  H01L27/11578 ,  H01L27/11568 ,  H01L27/11565

    Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.

    Memory devices
    7.
    发明授权
    Memory devices 有权

    公开(公告)号：US10128263B2

    公开(公告)日：2018-11-13

    申请号：US15224238

    申请日：2016-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Cheon Baek ,  Young Woo Kim ,  Dong Sik Lee ,  Min Yong Lee ,  Woong Seop Lee

    IPC: H01L29/76 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/06

    Abstract: A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers.

    Semiconductor device including multi-stack structure
    8.
    发明授权
    Semiconductor device including multi-stack structure 有权

    公开(公告)号：US11882701B2

    公开(公告)日：2024-01-23

    申请号：US17333407

    申请日：2021-05-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Cheon Baek

    IPC: H10B43/27 ,  H01L29/66 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

    CPC classification number: H10B43/27 ,  H01L29/66833 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

    Abstract: A semiconductor device includes a substrate having a cell region and a connection region adjacent to the cell region. A lower stack structure and an upper stack structure are disposed on the substrate. A channel structure is provided to pass through the upper stack structure and the lower stack structure. A distance between a lower extension line portion included in an uppermost one of a plurality of lower interconnection layers and an upper extension line portion included in a lowermost one of a plurality of upper interconnection layers is less than a distance between a lower gate electrode portion included in the uppermost one of the plurality of lower interconnection layers and an upper gate electrode portion included in the lowermost one of the plurality of upper interconnection layers.

    Three-dimensional semiconductor device
    9.
    发明授权
    Three-dimensional semiconductor device 有权

    公开(公告)号：US11476265B2

    公开(公告)日：2022-10-18

    申请号：US16401205

    申请日：2019-05-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Cheon Baek

    IPC: H01L27/11556 ,  H01L27/02 ,  G11C5/06 ,  H01L27/11582

    Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion. The intermediate interlayer insulation layer has the same thickness as that of an interlayer insulation layer adjacent in the vertical direction.

    SEMICONDUCTOR DEVICES INCLUDING CHANNEL STRUCTURES
    10.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING CHANNEL STRUCTURES 审中-公开

    公开(公告)号：US20200185402A1

    公开(公告)日：2020-06-11

    申请号：US16454293

    申请日：2019-06-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YOON HWAN SON ,  Seok Cheon Baek ,  Ji Sung Cheon

    IPC: H01L27/11578 ,  H01L27/11565 ,  H01L27/11568

    Abstract: A semiconductor device may include a substrate and a stacked structure in which a plurality of insulating layers and a plurality of interconnection layers are alternately stacked on the substrate. An isolation region may cross the stacked structure in a first direction. A plurality of first structures may extend into the stacked structure in a second direction perpendicular to the first direction. A plurality of first patterns may extend into the stacked structure in the second direction in the isolation region. Bottoms of the plurality of first patterns may be farther from an upper surface of the substrate than bottoms of the plurality of channel structures.

Patent Agency Ranking