公开(公告)号：US20240079040A1

公开(公告)日：2024-03-07

申请号：US18225908

申请日：2023-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang

IPC: G11C11/16

CPC classification number: G11C11/1655 ,  G11C11/161 ,  G11C11/1657

Abstract: A memory device including a three-dimensional racetrack and an operating method of the memory device are provided. The memory device includes a first racetrack, a first transistor, a first domain index controller, a bit line driver, a plurality of first magnetic tunnel junction (MTJ) elements, a plurality of first cell transistors, and a source line driver.

公开(公告)号：US20220108159A1

公开(公告)日：2022-04-07

申请号：US17319679

申请日：2021-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang ,  Jaewon Yang

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16 ,  G06F7/544

Abstract: A compressed-truncated singular value decomposition (C-TSVD) based crossbar array apparatus is provided. The C-TSVD based crossbar array apparatus may include an original crossbar array in an m×n matrix having row input lines and column output lines and including cells of a resistance memory device, or two partial crossbar arrays obtained by decomposing the original crossbar array based on C-TSVD, an analog to digital converter (ADC) that converts output values of column output lines of sub-arrays obtained through array partitioning, an adder that sums up results of the ADC to correspond to the column output lines, and a controller that controls application of the original crossbar array or the two partial crossbar arrays. Input values are input to the row input lines, a weight is multiplied by the input values and accumulated results are output as output values of the column output lines.

公开(公告)号：US08824195B2

公开(公告)日：2014-09-02

申请号：US14044581

申请日：2013-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang

IPC: G11C11/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: Phase-change memory devices are provided. A phase-change memory device may include a substrate and a conductive region on the substrate. Moreover, the phase-change memory device may include a lower electrode on the conductive region. The lower electrode may include a metal silicide layer on the conductive region, and a metal silicon nitride layer including a resistivity of about 10 to about 100 times that of the metal silicide layer. Moreover, the lower electrode may include a metal oxide layer between the metal silicon nitride layer and the metal silicide layer. The metal oxide layer may include a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer. The phase-change memory device may also include a phase-change layer and an upper electrode on the lower electrode.

Abstract translation: 提供了相变存储器件。 相变存储器件可以包括衬底和衬底上的导电区域。 此外，相变存储器件可以在导电区域上包括下电极。 下部电极可以包括在导电区域上的金属硅化物层，以及金属氮化硅层，其电阻率约为金属硅化物层的约10至约100倍。 此外，下电极可以在金属氮化硅层和金属硅化物层之间包括金属氧化物层。 金属氧化物层可以包括大于金属硅化物层的电阻率并且小于金属氮化硅层的电阻率。 相变存储器件还可以包括下电极上的相变层和上电极。