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    Magnetoresistive random access memory (MRAM) with end of life margin sensor
    3.
    发明授权
    Magnetoresistive random access memory (MRAM) with end of life margin sensor 有权

    公开(公告)号：US12094510B2

    公开(公告)日：2024-09-17

    申请号：US17807518

    申请日：2022-06-17

    Applicant: NXP USA, Inc.

    Inventor： Anirban Roy ,  Thomas Stephen Harp ,  Nihaar N. Mahatme ,  Jon Scott Choy

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1677

    Abstract: A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.

    Memory and electronic device
    4.
    发明授权
    Memory and electronic device 有权

    公开(公告)号：US12073863B2

    公开(公告)日：2024-08-27

    申请号：US17387588

    申请日：2021-07-28

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Yue Pan ,  Yanxiang Liu ,  Stephane Badel

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673

    Abstract: A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.

    Magnetic junction memory device and writing method thereof
    8.
    发明授权
    Magnetic junction memory device and writing method thereof 有权

    公开(公告)号：US12014763B2

    公开(公告)日：2024-06-18

    申请号：US17882790

    申请日：2022-08-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan Kyung Kim ,  Ji Yean Kim ,  Hyun Taek Jung ,  Ji Eun Kim ,  Tae Seong Kim ,  Sang-Hoon Jung ,  Jae Wook Joo

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673

    Abstract: Magnetic junction memory devices and methods for writing data to memory devices are provided. The magnetic junction memory device includes a first memory bank including first magnetic junction memory cells, a first local write driver adjacent to the first memory bank, connected to global data lines, the first local write driver configured to write data to the first magnetic junction memory cells via local data lines, a second memory bank adjacent to the first memory bank and including second magnetic junction memory cells, a second local write driver adjacent to the second memory bank, connected to the global data lines, the second local write driver configured to write data to the second magnetic junction memory cells via local data lines, and a global write driver configured to provide first and second write data to the first and second local write driver, respectively, via the global data lines.

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