公开(公告)号：US20240047419A1

公开(公告)日：2024-02-08

申请号：US18309149

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwoo KIM

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/18 ,  H10B80/00 ,  H01L24/48 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2224/73257 ,  H01L2924/181 ,  H01L2224/48155

Abstract: A semiconductor package may include a substrate including a connection circuit, a redistribution structure, and a chip structure on the redistribution structure. The redistribution structure may include a rear redistribution layer electrically connected to the connection circuit, a first semiconductor chip between rear and front redistribution portions and electrically connection to a front redistribution layer of the front redistribution portion, a first molded portion covering at least a portion of the first semiconductor chip, and a first through-via passing through the first molded portion and electrically connecting the front and the rear redistribution layers. The chip structure may include a wiring portion having a wiring layer electrically connected to the front redistribution layer, second and third semiconductor chips on the wiring portion and electrically connected to the wiring layer, and a second molded portion covering at least a portion of each of the second and third semiconductor chips.

公开(公告)号：US20220069100A1

公开(公告)日：2022-03-03

申请号：US17231126

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoontae HWANG ,  Wandon KIM ,  Geunwoo KIM ,  Heonbok LEE ,  Taegon KIM ,  Hanki LEE

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

公开(公告)号：US20210134793A1

公开(公告)日：2021-05-06

申请号：US16860279

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Yoon Tae HWANG ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522 ,  H01L29/49

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US20210104524A1

公开(公告)日：2021-04-08

申请号：US16898719

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae HWANG ,  Sunjung LEE ,  Heonbok LEE ,  Geunwoo KIM ,  Wandon KIM

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US20200217917A1

公开(公告)日：2020-07-09

申请号：US16737219

申请日：2020-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoub RYU ,  Geunwoo KIM ,  Changhyun KIM ,  Soohoon LEE ,  Byoungkab CHOI

IPC: G01S3/801 ,  H04M1/03 ,  G01S3/808

Abstract: Provided is an electronic apparatus. The electronic apparatus includes an audio receiver configured to obtain an audio signal of sound output by an external object; a sensor configured to sense a posture of the electronic apparatus; a display; and a processor configured to, based on the audio signal that is obtained by the audio receiver, determine a direction in which the external object is located with respect to the electronic apparatus, and control the display to display a graphical object that corresponds to the external object based on the posture of the electronic apparatus sensed by the sensor and the direction in which the external object is located.