公开(公告)号：US20230091131A1

公开(公告)日：2023-03-23

申请号：US17739329

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Jiwon SHIN ,  Donguk KWON ,  Wooram MYUNG ,  Kwangbok WOO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Provided is a mounting substrate for a semiconductor package, including a substrate having an upper surface and a lower surface opposite to each other, the substrate including a plurality of insulation layers and wirings in the plurality of insulation layers, first substrate pads and second substrate pads on the upper surface in a chip mounting region of the mounting surface, heat absorbing pads on the upper surface in a peripheral region of the mounting surface adjacent to the chip mounting region, and connection lines in the substrate, the connection lines being configured to thermally couple the heat absorbing pads and the second substrate pads to each other.

公开(公告)号：US20220139910A1

公开(公告)日：2022-05-05

申请号：US17578982

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Yoon Tae HWANG ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US20250096134A1

公开(公告)日：2025-03-20

申请号：US18650288

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwoo KIM ,  Hyunwoo KANG ,  Mingyu KIM ,  Wandon KIM ,  Wonkeun CHUNG ,  Hyoseok CHOI

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

公开(公告)号：US20230118906A1

公开(公告)日：2023-04-20

申请号：US18085871

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoontae HWANG ,  Wandon KIM ,  Geunwoo KIM ,  Heonbok LEE ,  Taegon KIM ,  Hanki LEE

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285 ,  H01L29/08 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

公开(公告)号：US20230012516A1

公开(公告)日：2023-01-19

申请号：US17672033

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoontae HWANG ,  Geunwoo KIM ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L29/417 ,  H01L29/45 ,  H01L23/522

Abstract: An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

公开(公告)号：US20250125280A1

公开(公告)日：2025-04-17

申请号：US18760146

申请日：2024-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejun KIM ,  Geunwoo KIM

IPC: H01L23/552 ,  H01L21/285 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package may include: a wiring structure having a structure in which at least one insulating layer and at least one wiring layer are alternately stacked; a semiconductor chip disposed to vertically overlap the wiring structure; and a conductive shielding layer accommodating the semiconductor chip, and covering a portion of a side surface of the wiring structure to be connected to a ground of the at least one wiring layer, wherein the other portion of the side surface of the wiring structure may not be covered by the conductive shielding layer.

公开(公告)号：US20250079279A1

公开(公告)日：2025-03-06

申请号：US18761415

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo KIM ,  Taehwan KIM ,  Taejun KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/528 ,  H01L23/552 ,  H05K1/11

Abstract: An electronic device includes a main board; a semiconductor package disposed on the main board and mounted via a plurality of conductive connection members; and an electromagnetic shielding member covering an upper surface and side surfaces of the semiconductor package. The plurality of conductive connection members includes: a plurality of signal connection balls disposed on a middle region of a lower surface of the semiconductor package and having a first diameter; and a plurality of electromagnetic shielding balls spaced apart from each other along an edge of the lower surface of the semiconductor package, the electromagnetic shielding balls surrounding the middle region and having a second diameter smaller than the first diameter.

公开(公告)号：US20230178476A1

公开(公告)日：2023-06-08

申请号：US17864716

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunwoo KANG ,  Yoontae HWANG ,  Geunwoo KIM ,  Sunghwan KIM ,  Junki PARK

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76831 ,  H01L23/53266

Abstract: An integrated circuit device includes a conductive region disposed on a substrate, an insulating structure including a contact hole disposed in the conductive region and extending from the conductive region in a vertical direction, a local capping pattern having an outer sidewall in contact with an upper portion of an inner wall of the contact hole and an inner sidewall facing an inside of the contact hole and having a width gradually increasing in a horizontal direction away from the substrate, and a conductive plug passing through the insulating structure through the contact hole in the vertical direction, having a lower sidewall in contact with the insulating structure and an upper sidewall in contact with the local capping pattern, and including a first metal.

公开(公告)号：US20230007088A1

公开(公告)日：2023-01-05

申请号：US17940444

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwoo KIM ,  Md. Imtiaz HOSSAIN ,  Muhammad Mushfiqul ISLAM ,  Towhidul ISLAM

IPC: H04L67/141 ,  H04L67/1095 ,  H04L65/40 ,  H04L47/70 ,  G06F3/14

Abstract: An electronic device includes a first communication module, a second communication module, a display, a processor, and a memory storing instructions causing the processor to receive, from an external electronic device connected via the first communication module, first data related to a first screen on which resources of the external electronic device are configured in accordance with a graphic environment of the electronic device, output the first screen on the display, request the external electronic device to execute a selected first resource, receive, from the external electronic device, a request for obtaining second data related to the first resource, connect to the network via the second communication module to obtain the second data, transmit the obtained second data to the external electronic device, receive, from the external electronic device, third data related to a second screen configured using the second data, and output the second screen on the display.

公开(公告)号：US20220157954A1

公开(公告)日：2022-05-19

申请号：US17588670

申请日：2022-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Tae HWANG ,  Wandon KIM ,  Geunwoo KIM

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.