Semiconductor structure utilizing empty and filled wells
    21.
    发明授权
    Semiconductor structure utilizing empty and filled wells 有权
    利用空和填充井的半导体结构

    公开(公告)号:US07863681B1

    公开(公告)日:2011-01-04

    申请号:US12545024

    申请日:2009-08-20

    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

    Abstract translation: 绝缘栅场效应晶体管(100,100V,140,150,150V,160,170,170V,180,180V,190,210,210W,220,220U,220V,220W,380或480)具有 低于其源极/漏极区(104或264)的垂直掺杂剂分布,用于减小源极/漏极区与邻接体材料(108或268)之间的pn结的寄生电容。 特别地,限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区(102或262)设置的更重掺杂的凹穴部分(120或280)。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

    Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
    22.
    发明授权
    Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications 有权
    具有特别适用于模拟应用的场效应晶体管的半导体架构的制造

    公开(公告)号:US07838369B2

    公开(公告)日:2010-11-23

    申请号:US11981355

    申请日:2007-10-31

    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

    Abstract translation: 制造绝缘栅场效应晶体管(100,100V,140,150,150V,160,170,170V,180,180V,190,210,210W,220,220U,220V,220W,380或480) 以便具有低于其源极/漏极区的一个(104或264)的低破坏垂直掺杂剂轮廓,用于减小沿着该源极/漏极区与邻接主体材料(108或268)之间的pn结的寄生电容。 特别地,限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的物体 - 物质位置之前至少增加10倍,不超过上部的10倍 半导体表面比该源/漏区。 主体材料优选地设置有沿着另一个源极/漏极区(102或262)设置的更加重掺杂的凹穴部分(120或280)。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

    Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor
    23.
    发明申请
    Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor 审中-公开
    具有扩展漏极场效应晶体管的半导体结构的配置和制造

    公开(公告)号:US20100244152A1

    公开(公告)日:2010-09-30

    申请号:US12382976

    申请日:2009-03-27

    Abstract: An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other. The IGFET's operating characteristics are stable with operational time.

    Abstract translation: 扩展漏极绝缘栅场效应晶体管(104或106)包含由第一阱的一部分构成的沟道(322或362)区域横向隔开的第一和第二源/漏区324和184B或364和186B, 区域(184A或186A)。 栅极电介质层(344或384)覆盖在沟道区上。 栅电极(346或386)覆盖沟道区上方的栅介质层。 第一个源/漏区通常是源。 第二S / D区(通常为漏极)由第二阱区(184B或186B)构成。 半导体本体的阱分离部分186A或186B / 212U)在阱区之间延伸,并且比每个阱区域轻掺杂。 阱区域的配置导致半导体本体的IGFET的部分中的最大电场远低于上半导体表面,通常处于或接近阱区彼此最接近的位置。 IGFET的运行特性在运行时间稳定。

    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone
    24.
    发明申请
    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone 有权
    具有不对称场效应晶体管的半导体结构的配置和制造,沿着源/漏区具有定制的口袋部分

    公开(公告)号:US20100244147A1

    公开(公告)日:2010-09-30

    申请号:US12382967

    申请日:2009-03-27

    Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

    Abstract translation: 沿着半导体主体的上表面设置的非对称绝缘栅场效应晶体管(100U或102U)包含由沟道区(244或284)横向隔开的第一和第二源/漏区(240和242或280和282) 的晶体管的主体材料。 栅电极(262或302)覆盖在沟道区上方的栅介电层(260或300)。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分(250或290)在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置(PH-1-PH-3)处达到多个局部最大值(316-1-316-3)。 通常实施定制,使得袋部分的垂直掺杂剂分布在上半导体表面附近相对平坦。 结果,晶体管具有减小的漏电流。

    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics
    26.
    发明授权
    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics 有权
    其中类似极性绝缘栅场效应晶体管具有多个垂直体掺杂浓度最大值和不同晕圈特征的半导体结构

    公开(公告)号:US07701005B1

    公开(公告)日:2010-04-20

    申请号:US11974751

    申请日:2007-10-15

    Abstract: Each of a pair of differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones (60 or 80) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion (100/102 or 104) extends along both source/drain zones of one of the transistors. Another pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

    Abstract translation: 半导体结构中的一对不同构造的相同极性的绝缘栅场效应晶体管(40或42和240或242)中的每一个具有半导体主体材料的沟道区,覆盖沟道区的栅介质层和 覆盖栅介电层的栅电极。 对于每个晶体管,主体材料的净掺杂剂浓度在沟道表面耗尽区下方达到多个局部地下极大值,并且大部分覆盖在沟道区上方的所有栅电极材料。 晶体管具有与主体材料相同的导电类型的源极/漏极区域(60或80)以及与主体材料相同的导电类型的卤素口袋部分。 一个口袋部分(100/102或104)沿着一个晶体管的源极/漏极区域延伸。 另一个口袋部分(244或246)沿着另一个晶体管的源极/漏极区域中的一个较大地延伸,使得它是不对称的。

    Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone
    28.
    发明授权
    Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone 有权
    其中互补场效应晶体管在低于至少一个源极/漏极区的每个都具有低破坏的体掺杂剂分布的半导体结构的制造

    公开(公告)号:US07419863B1

    公开(公告)日:2008-09-02

    申请号:US11215537

    申请日:2005-08-29

    Abstract: Complementary IGFETs (210W and 220W or 530 and 540) are fabricated so that the body dopant concentration in each IGFET decreases by at least 10 in moving from a subsurface location in the body material of that IGFET up to one of its source/drain zones. Semiconductor dopant, typically a fast-diffusing species such as aluminum, is introduced into starting semiconductor material to form a relatively uniformly doped region that serves as body material (108) for one of the IGFETs. A remaining part of the starting material serves as body material (268) for the other IGFET. Well dopant is introduced into the body material of each IGFET for establishing the requisite body dopant profile. Alternatively, a cavity is formed through an initial structure having body material (108) doped in the preceding way for one of the IGFETs. Semiconductor material is introduced into the cavity to form the body material (568) for the other IGFET.

    Abstract translation: 制造互补IGFET(210W和220W或530和540),使得每个IGFET中的身体掺杂剂浓度从该IGFET的体材料的地下位置移动到其源极/漏极之一时减少至少10个 区域。 通常将诸如铝的快速扩散物质的半导体掺杂物引入起始半导体材料中以形成用作IGFET之一的主体材料(108)的相对均匀的掺杂区域。 起始材料的剩余部分用作另一个IGFET的主体材料(268)。 将良好的掺杂剂引入每个IGFET的主体材料中以建立必需的体掺杂物分布。 或者,通过具有以前述方式掺杂的IGFET的主体材料(108)的初始结构形成空腔。 将半导体材料引入空腔中以形成其它IGFET的主体材料(568)。

    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
    30.
    发明授权
    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone 有权
    具有不对称场效应晶体管的半导体结构的配置和制造,沿着源/漏区具有定制的口袋部分

    公开(公告)号:US08415752B2

    公开(公告)日:2013-04-09

    申请号:US13348577

    申请日:2012-01-11

    Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

    Abstract translation: 沿着半导体主体的上表面设置的非对称绝缘栅场效应晶体管(100U或102U)包含由沟道区(244或284)横向隔开的第一和第二源/漏区(240和242或280和282) 的晶体管的主体材料。 栅电极(262或302)覆盖在沟道区上方的栅介电层(260或300)。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分(250或290)在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置(PH-1-PH-3)处达到多个局部最大值(316-1-316-3)。 通常实施定制,使得袋部分的垂直掺杂剂分布在上半导体表面附近相对平坦。 结果,晶体管具有减小的漏电流。

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