Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
    2.
    发明授权
    Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone 有权
    具有不对称场效应晶体管的半导体结构的制造,沿着源/漏区具有定制的口袋部分

    公开(公告)号:US08163619B2

    公开(公告)日:2012-04-24

    申请号:US12382967

    申请日:2009-03-27

    IPC分类号: H01L21/336

    摘要: An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.

    摘要翻译: 沿着半导体主体的上表面设置非对称绝缘栅场效应晶体管(100U或102U),以便具有由沟道区横向隔开的第一和第二源/漏区(240和242或280和282) 244或284)晶体管的主体材料。 栅电极(262或302)覆盖在沟道区上方的栅介电层(260或300)。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分(250或290)在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置(PH-1-PH-3-NH-3)处达到多个局部最大值。 这通常使得晶体管具有减小的电流泄漏。

    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone
    3.
    发明申请
    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone 有权
    具有不对称场效应晶体管的半导体结构的配置和制造,沿着源/漏区具有定制的口袋部分

    公开(公告)号:US20100244147A1

    公开(公告)日:2010-09-30

    申请号:US12382967

    申请日:2009-03-27

    IPC分类号: H01L29/78 H01L21/336

    摘要: An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

    摘要翻译: 沿着半导体主体的上表面设置的非对称绝缘栅场效应晶体管(100U或102U)包含由沟道区(244或284)横向隔开的第一和第二源/漏区(240和242或280和282) 的晶体管的主体材料。 栅电极(262或302)覆盖在沟道区上方的栅介电层(260或300)。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分(250或290)在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置(PH-1-PH-3)处达到多个局部最大值(316-1-316-3)。 通常实施定制,使得袋部分的垂直掺杂剂分布在上半导体表面附近相对平坦。 结果,晶体管具有减小的漏电流。

    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
    6.
    发明授权
    Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone 有权
    具有不对称场效应晶体管的半导体结构的配置和制造,沿着源/漏区具有定制的口袋部分

    公开(公告)号:US08415752B2

    公开(公告)日:2013-04-09

    申请号:US13348577

    申请日:2012-01-11

    IPC分类号: H01L29/78

    摘要: An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

    摘要翻译: 沿着半导体主体的上表面设置的非对称绝缘栅场效应晶体管(100U或102U)包含由沟道区(244或284)横向隔开的第一和第二源/漏区(240和242或280和282) 的晶体管的主体材料。 栅电极(262或302)覆盖在沟道区上方的栅介电层(260或300)。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分(250或290)在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置(PH-1-PH-3)处达到多个局部最大值(316-1-316-3)。 通常实施定制,使得袋部分的垂直掺杂剂分布在上半导体表面附近相对平坦。 结果,晶体管具有减小的漏电流。

    Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket
    7.
    发明授权
    Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket 有权
    使用空穴与源极/漏极延伸部分或/和晕圈组合的场效应晶体管的结构和制造

    公开(公告)号:US08410549B2

    公开(公告)日:2013-04-02

    申请号:US12382968

    申请日:2009-03-27

    IPC分类号: H01L29/66

    摘要: Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E). Alternatively or additionally, a more heavily doped pocket portion (250 or 290) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.

    摘要翻译: 对称和非对称的绝缘栅场效应晶体管(IGFET)适用于为模拟和数字应用(包括混合信号应用)提供IGFET的半导体制造平台,利用空井区域实现高性能。 相对少量的半导体阱掺杂剂在每个空的孔的顶部附近。 每个IGFET(100,102,112,114,124或126)具有由空井(180,182,192,194,204或206)的主体材料的通道区横向隔开的一对源/排出区 )。 栅极电极覆盖在沟道区上方的栅极电介质层。 每个源/漏区(240,242,282,282,520,522,550,552,720,722,752或752)具有主要部分(240M,242M,280M,282M,520M,522M,550M, 552M,720M,722M,752M或752M)和更轻掺杂的侧向延伸部(240E,242E,280E,282E,520E,522E,550E,552E,720E,722E,752E或752E)。 替代地或另外地,主体材料的更加掺杂的凹穴部分(250或290)沿着源极/漏极区域中的一个延伸。 当存在时,口袋部分通常使IGFET成为非对称装置。

    Configuration and fabrication of semiconductor structure using empty and filled wells
    9.
    发明授权
    Configuration and fabrication of semiconductor structure using empty and filled wells 有权
    使用空和填充井的半导体结构的配置和制造

    公开(公告)号:US08304835B2

    公开(公告)日:2012-11-06

    申请号:US12382973

    申请日:2009-03-27

    IPC分类号: H01L29/36

    摘要: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

    摘要翻译: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管(IGFET)不同地使用的空阱区域和填充阱区域的组合,以实现期望的电子 特点 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET(100,102,112,114,124和126)利用空井(180,182,192,194,204和206)实现期望的晶体管特性。 其它IGFET(108,110,116,118,120和122)利用填充的孔(188,190,196,198,200和202)实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET,电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用,包括混合信号应用。

    Configuration and fabrication of semiconductor structure using empty and filled wells
    10.
    发明申请
    Configuration and fabrication of semiconductor structure using empty and filled wells 有权
    使用空和填充井的半导体结构的配置和制造

    公开(公告)号:US20100244128A1

    公开(公告)日:2010-09-30

    申请号:US12382973

    申请日:2009-03-27

    摘要: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

    摘要翻译: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管(“IGFET”)不同地使用的空阱区域和填充阱区域的组合,以实现 所需的电子特性。 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET(100,102,112,114,124和126)利用空井(180,182,192,194,204和206)实现期望的晶体管特性。 其它IGFET(108,110,116,118,120和122)利用填充的孔(188,190,196,198,200和202)实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET,电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用,包括混合信号应用。