公开(公告)号：US20110057315A1

公开(公告)日：2011-03-10

申请号：US12943679

申请日：2010-11-10

申请人： Shenqing FANG ,  Wenmei LI

发明人： Shenqing FANG ,  Wenmei LI

IPC分类号： H01L23/48

CPC分类号： H01L23/522 ,  H01L21/76816 ,  H01L23/485 ,  H01L27/1052 ,  H01L27/11529 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.

摘要翻译： 在一个实施例中，集成电路存储器件包括衬底和连续地设置在衬底上的第一和第二级间介电层。 外围设备中的一个或多个触点延伸穿过第一层间电介质层到相应的部件。 一个或多个通孔和多个虚拟通孔延伸穿过周边区域中的第二层间电介质层。 一个或多个外围通孔中的每一个延伸到相应的外围触点。 外围的虚拟通孔位于外围通孔附近。

公开(公告)号：US20110012191A1

公开(公告)日：2011-01-20

申请号：US12891481

申请日：2010-09-27

申请人： Shenqing FANG ,  Kuo-Tung CHANG ,  Tim THURGATE ,  YouSeok SUH ,  Allison HOLBROOK

发明人： Shenqing FANG ,  Kuo-Tung CHANG ,  Tim THURGATE ,  YouSeok SUH ,  Allison HOLBROOK

IPC分类号： H01L29/792 ,  H01L21/76

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

摘要翻译： 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。 在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。 对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。 然后在核心单元之间部分蚀刻捕获层。 进行捕获层上的氧化物的偏移。 并形成顶部氧化物。 顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

公开(公告)号：US20100078814A1

公开(公告)日：2010-04-01

申请号：US12240627

申请日：2008-09-29

申请人： Alok Nandini ROY ,  Zubin P. PATEL ,  Shenqing FANG

发明人： Alok Nandini ROY ,  Zubin P. PATEL ,  Shenqing FANG

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/32051 ,  H01L21/76825 ,  H01L21/76831 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for manufacturing a semiconductor device including a low dielectric constant porous material layer. Ions are implanted into the low dielectric constant porous material layer which thereby provides the porous material layer with sufficient mechanical strength for withstanding semiconductor manufacturing processes. The ions implanted in the porous material layer further facilitate disposition of a conductive layer on the porous material layer.

摘要翻译： 一种用于制造包括低介电常数多孔材料层的半导体器件的系统和方法。 将离子注入到低介电常数多孔材料层中，从而为多孔材料层提供足够的机械强度以耐受半导体制造工艺。 注入多孔材料层中的离子进一步有助于在多孔材料层上布置导电层。

公开(公告)号：US20090268500A1

公开(公告)日：2009-10-29

申请号：US12111886

申请日：2008-04-29

申请人： Shenqing FANG ,  Jihwan CHOI ,  Connie WANG ,  Eunha KIM

发明人： Shenqing FANG ,  Jihwan CHOI ,  Connie WANG ,  Eunha KIM

IPC分类号： G11C5/06 ,  H01L21/8234

CPC分类号： H01L27/11573 ,  G11C5/063 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/665 ,  H01L29/66507

摘要： Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.

摘要翻译： 公开了用于降低集成电路存储器件的字线中的电阻的方法和结构。 在一个实施例中，该方法包括在相应数量的字线上形成多列多晶硅，形成与字线相关联的核心晶体管结和外围晶体管结，对外围晶体管结执行盐化处理，并对 多晶硅从字线低电阻。

公开(公告)号：US20090090953A1

公开(公告)日：2009-04-09

申请号：US12327641

申请日：2008-12-03

申请人： Shenqing FANG ,  Hiroyuki OGAWA ,  Kuo-Tung CHANG ,  Pavel FASTENKO ,  Kazuhiro MIZUTANI ,  Zhigang WANG

发明人： Shenqing FANG ,  Hiroyuki OGAWA ,  Kuo-Tung CHANG ,  Pavel FASTENKO ,  Kazuhiro MIZUTANI ,  Zhigang WANG

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/2652 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation.

摘要翻译： 本发明的实施例公开了一种存储器件，其具有具有促进直线字线的源极触点的闪存单元阵列及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 在形成隧道氧化物层和第一多晶硅层之后，源极列注入n型掺杂剂。 植入的源极柱耦合到耦合到与阵列中的存储器单元相关联的多个源极区域的多个公共源极线。 源极触点耦合到植入源极柱，用于提供与多个源极区域的电耦合。 源触点与一排漏极触点共线，该排触点耦合到与一行存储器单元相关联的漏极区。 与漏极触点排共线的源触点的布置允许直线字线形成。