公开(公告)号：US08531872B2

公开(公告)日：2013-09-10

申请号：US13350340

申请日：2012-01-13

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

IPC分类号： G11C11/00

CPC分类号： G11C11/417

摘要： High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 实现了高制造成品率，补偿了CMOS·SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据确定结果被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS·SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置电压施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US08107279B2

公开(公告)日：2012-01-31

申请号：US12563231

申请日：2009-09-21

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

IPC分类号： G11C11/00

CPC分类号： G11C11/417

摘要： High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS.SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS.SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 实现了高制造产量，并补偿了CMOS.SRAM中每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US07616519B2

公开(公告)日：2009-11-10

申请号：US11812193

申请日：2007-06-15

申请人： Shigenobu Komatsu ,  Masanao Yamaoka

发明人： Shigenobu Komatsu ,  Masanao Yamaoka

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/18 ,  G11C11/412

摘要： The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.

摘要翻译： 本发明提供一种能够在安装有时间分配虚拟多端口存储器等的半导体集成电路装置上实现面积缩小的技术。 通过提供包括单端口存储器，用于多个端口的数据锁存电路，用于选择要连接到单端口存储器的端口的选择器，时间共享控制信号生成电路等，其中内部的操作终止信号 将单端口存储器（字线上升信号，用于数据读取的读出放大器驱动信号等）输入到时间共享控制信号发生电路，以产生用于单端口存储器的端口切换控制信号和操作控制信号 可以实现具有减小面积的虚拟多端口存储器的时间分配，这不需要新的时间分配控制的时钟发生电路。

公开(公告)号：US07596013B2

公开(公告)日：2009-09-29

申请号：US11943495

申请日：2007-11-20

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

IPC分类号： G11C11/00

CPC分类号： G11C11/417

摘要： High manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 实现了高制造产量，并补偿了CMOS.SRAM中每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US07385870B2

公开(公告)日：2008-06-10

申请号：US11812596

申请日：2007-06-20

申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。

公开(公告)号：US20070247952A1

公开(公告)日：2007-10-25

申请号：US11812596

申请日：2007-06-20

申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

公开(公告)号：US20060133180A1

公开(公告)日：2006-06-22

申请号：US11353967

申请日：2006-02-15

申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

公开(公告)号：US07031220B2

公开(公告)日：2006-04-18

申请号：US10927052

申请日：2004-08-27

申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。

公开(公告)号：US20080247258A1

公开(公告)日：2008-10-09

申请号：US12117804

申请日：2008-05-09

申请人： Noriyoshi WATANABE ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi WATANABE ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。

公开(公告)号：US07251182B2

公开(公告)日：2007-07-31

申请号：US11353967

申请日：2006-02-15

申请人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

发明人： Noriyoshi Watanabe ,  Noriaki Maeda ,  Masanao Yamaoka ,  Yoshihiro Shinozaki

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2227

摘要： A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

摘要翻译： 功率控制部的MOS晶体管的待机时的漏电流急剧下降，能够实现消耗功率的降低。 存储器模块具有功率控制部分。 当没有选择任何存储器垫时，功率控制部分将电源电压停止到未选择的存储器垫，字驱动器，输入输出电路，控制电路和输出电路。 在存储器模块的待机时，功率控制部分停止对功率控制部分，控制电路，预解码器电路和输入电路的电源。 以这种方式，可以显着降低在待机时功率控制部分的MOS晶体管的漏电流。