公开(公告)号：US5535170A

公开(公告)日：1996-07-09

申请号：US439558

申请日：1995-05-11

申请人： Yukinaga Imamura ,  Kazuya Yamanaka ,  Shiro Hosotani ,  Minobu Yazawa

发明人： Yukinaga Imamura ,  Kazuya Yamanaka ,  Shiro Hosotani ,  Minobu Yazawa

IPC分类号： G06F12/04 ,  G06F5/10 ,  G11C7/00 ,  G11C7/10 ,  G11C8/04 ,  G11C11/401 ,  G11C11/405 ,  G11C8/00

CPC分类号： G11C7/1018 ,  G11C8/04

摘要： y memory blocks are connected in series. A row select signal is output to each memory block from a row address pointer corresponding to a plurality of memory circuits in one memory block. Similarly, a column select signal is output to each memory block from a column address pointer corresponding to a plurality of memory circuits in one memory block. Therefore, the same row and column select signals are applied to each memory block, whereby data is sequentially input/output for every memory block. Thus, the circuit complexity of the row and column address pointers can be reduced.

摘要翻译： y内存块串联连接。 行选择信号从与一个存储器块中的多个存储器电路对应的行地址指针输出到每个存储器块。 类似地，列选择信号从与一个存储器块中的多个存储器电路相对应的列地址指针输出到每个存储器块。 因此，对每个存储块应用相同的行和列选择信号，从而每个存储器块依次输入/输出数据。 因此，可以减少行和列地址指针的电路复杂度。

公开(公告)号：US5349354A

公开(公告)日：1994-09-20

申请号：US29426

申请日：1993-03-09

申请人： Masao Ito ,  Shiro Hosotani

发明人： Masao Ito ,  Shiro Hosotani

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/144 ,  H03M1/365

摘要： An improved serial-parallel type A/D converter is disclosed herein. A gate circuit 7 applies signals S11' to S14' provided from an encoder 3 only in a fine comparison period to switching circuits 11 to 14 as switching control signals S11 to S14. In the fine comparison period, one switching circuit is turned on, so that a fine comparison voltage is applied to voltage comparators 21 to 23. Since all of the switching circuits are turned off in a coarse comparison period, correct coarse comparison voltage is provided from a reference voltage generating circuit. As a result, a correct conversion in the coarse comparison period can be performed.

摘要翻译： 本文公开了一种改进的串并联型A / D转换器。 门电路7仅在精细比较期间将从编码器3提供的信号S11'应用于切换电路11至14作为切换控制信号S11至S14。 在精细的比较时段中，一个开关电路导通，使得精确的比较电压被施加到电压比较器21至23.由于所有的开关电路在粗略的比较周期中被关断，因此从 参考电压发生电路。 结果，可以进行粗略比较期间的正确转换。

公开(公告)号：US5140186A

公开(公告)日：1992-08-18

申请号：US631649

申请日：1990-12-21

申请人： Masao Ito ,  Shiro Hosotani

发明人： Masao Ito ,  Shiro Hosotani

IPC分类号： H03K5/08 ,  H03K5/24

CPC分类号： H03K5/249

摘要： A voltage comparator includes a coupling capacitor which receives at one terminal thereof two signals applied in a complementary fashion, an inverting amplifier having an input coupled to the other terminal of the coupling capacitor and having an output, and switch means coupled between the input and output of the inverting amplifier so as to be in parallel with the inverting amplifier. The duration of an auto-zeroing interval during which the switch means is conductive is maintained constant regardless of the period of the ON-OFF operation of the switch means.

摘要翻译： 电压比较器包括耦合电容器，其在一个端子处接收以互补方式施加的两个信号，反相放大器具有耦合到耦合电容器的另一端并具有输出的输入，以及耦合在输入和输出之间的开关装置 的反相放大器，以便与反相放大器并联。 开关装置导通的自动归零间隔的持续时间保持恒定，而与开关装置的ON-OFF操作的周期无关。