公开(公告)号：US20180159498A1

公开(公告)日：2018-06-07

申请号：US15735477

申请日：2016-06-09

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/10

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20150179520A1

公开(公告)日：2015-06-25

申请号：US14416895

申请日：2013-07-08

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bernard Aspar ,  Chrystelle Lagahe Blanchard

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/683 ,  H01L21/268

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/7813 ,  H01L33/0079

Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.

Abstract translation: 制造半导体结构的方法包括将载体晶片结合在衬底上，去除衬底的至少一部分，通过载体晶片传输激光辐射并削弱衬底和载体晶片之间的结合，并将载体晶片与 基质。 其他方法包括在衬底上形成电路，在衬底中形成沟槽以限定非引线半导体管芯，将载体衬底接合在非引线半导体管芯上方，将激光辐射传输通过载体衬底并削弱未加掩模的半导体管芯与载体衬底之间的接合 并且将载体衬底与未折叠的半导体管芯分离。 一些方法包括使衬底的至少一部分变薄，使得多个未折叠的半导体管芯接合到载体衬底。