公开(公告)号：US20210058058A1

公开(公告)日：2021-02-25

申请号：US17075465

申请日：2020-10-20

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H03H3/10

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US09905531B2

公开(公告)日：2018-02-27

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/306 ,  H01L21/66

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

公开(公告)号：US11595020B2

公开(公告)日：2023-02-28

申请号：US16877309

申请日：2020-05-18

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H03H3/10 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H01L41/187 ,  H01L41/47 ,  H01L41/332 ,  H01L41/337 ,  H03H9/64

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US10886162B2

公开(公告)日：2021-01-05

申请号：US16090349

申请日：2017-03-30

Applicant: Soitec

Inventor： Arnaud Castex ,  Oleg Kononchuk

IPC: H01L21/322 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02

Abstract: A semiconductor-on-insulator substrate for use in RF applications, such as a silicon-on-insulator substrate, comprises a semiconductor top layer, a buried oxide layer and a passivation layer over a support substrate. In addition, a penetration layer is provided between the passivation layer and the silicon support substrate to ensure sufficient high resistivity below RF features and avoid increased migration of dislocations in the support substrate. RF devices may be fabricated on and/or in such a semiconductor-on-insulator substrate.

公开(公告)号：US10826459B2

公开(公告)日：2020-11-03

申请号：US15735477

申请日：2016-06-09

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/10 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H01L41/47 ,  H03H3/04 ,  H01L41/332 ,  H01L41/337 ,  H03H9/64

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20240396520A1

公开(公告)日：2024-11-28

申请号：US18790454

申请日：2024-07-31

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/64 ,  H10N30/072 ,  H10N30/073 ,  H10N30/082 ,  H10N30/086 ,  H10N30/853 ,  H10N35/01

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20240030883A1

公开(公告)日：2024-01-25

申请号：US17907247

申请日：2021-03-24

Applicant: Soitec

Inventor： Arnaud Castex ,  Laurence Doutre-Roussel ,  Eric Butaud ,  Brice Tavel

IPC: H03H3/08 ,  H10N30/073 ,  H10N30/082 ,  H10N30/086

CPC classification number: H03H3/08 ,  H10N30/073 ,  H10N30/082 ,  H10N30/086

Abstract: A method of manufacturing a piezoelectric structure comprises providing a substrate of piezoelectric material, providing a carrier substrate, depositing a dielectric bonding layer at a temperature lower than or equal to 300° C. on a single side of the substrate of piezoelectric material, a step of joining the substrate of piezoelectric material to the carrier substrate via the dielectric bonding layer, a thinning step for forming the piezoelectric structure, which comprises a layer of piezoelectric material joined to a carrier substrate.

公开(公告)号：US11637542B2

公开(公告)日：2023-04-25

申请号：US17075465

申请日：2020-10-20

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H01L41/08 ,  H03H3/04 ,  H03H9/64 ,  H01L41/312 ,  H01L41/313 ,  H01L41/187 ,  H03H3/10 ,  H01L41/47 ,  H01L41/332 ,  H01L41/337

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US09548202B2

公开(公告)日：2017-01-17

申请号：US14434624

申请日：2013-10-11

Applicant: Soitec

Inventor： Marcel Broekaart ,  Arnaud Castex

IPC: B32B37/00 ,  H01L21/18 ,  B32B37/10

CPC classification number: H01L21/187 ,  B32B37/0007 ,  B32B37/1009 ,  B32B2037/0092 ,  B32B2307/20 ,  B32B2457/14

Abstract: The disclosure relates to a method of bonding by molecular adhesion comprising the positioning of a first wafer and of a second wafer within a hermetically sealed vessel, the evacuation of the vessel to a first pressure lower than or equal to 400 hPa, the adjustment of the pressure in the vessel to a second pressure higher than the first pressure by introduction of a dry gas, and bringing the first and second wafers into contact, followed by the initiation of the propagation of a bonding wave between the two wafers, while maintaining the vessel at the second pressure.

Abstract translation: 本发明涉及一种通过分子粘合进行粘合的方法，包括将第一晶片和第二晶片定位在密封容器内，将容器排空至低于或等于400hPa的第一压力， 通过引入干燥气体将容器中的压力升至高于第一压力的第二压力，并使第一和第二晶片接触，随后在两个晶片之间引起粘结波的传播，同时保持容器 在第二个压力。

公开(公告)号：US20230275559A1

公开(公告)日：2023-08-31

申请号：US18302440

申请日：2023-04-18

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H10N30/072 ,  H10N30/073 ,  H10N30/00 ,  H10N30/853 ,  H03H3/10

CPC classification number: H03H9/02834 ,  H03H9/02574 ,  H03H3/04 ,  H10N30/072 ,  H10N30/073 ,  H10N30/1051 ,  H10N30/8542 ,  H03H3/10 ,  Y10T29/42 ,  H10N30/082

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.