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公开(公告)号：US20100100578A1
公开(公告)日：2010-04-22
申请号：US12253713
申请日：2008-10-17
申请人： Son Trong Dao , Juergen Georg Haess , Michael Klaus Kroener , Silvia Melitta Mueller , Jochen Preiss
发明人： Son Trong Dao , Juergen Georg Haess , Michael Klaus Kroener , Silvia Melitta Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/483
摘要： A distributed residue checking apparatus for a floating point unit having a plurality of functional elements performing floating-point operations on a plurality of operands. The distributed residue checking apparatus includes a plurality of residue generators which generate residue values for the operands and the functional elements, and a plurality of residue checking units distributed throughout the floating point unit. Each residue checking unit receives a first residue value and a second residue value from respective residue generators and compares the first residue value to the second residue value to determine whether an error has occurred in a floating-point operation performed by a respective functional element.
摘要翻译： 一种用于具有对多个操作数执行浮点运算的多个功能单元的浮点单元的分布式残留检查装置。 所述分布式残差检查装置包括生成所述操作数和所述功能元件的残差值的多个残差生成器，以及分布在所述浮点单元中的多个残差检查单元。 每个残差检查单元从相应的残差发生器接收第一残差值和第二残差值，并将第一残差值与第二残差值进行比较，以确定在由各个功能元件执行的浮点运算中是否发生了错误。
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22.发明授权公开(公告)号：US07490119B2
公开(公告)日：2009-02-10
申请号：US10733839
申请日：2003-12-11
CPC分类号： G06F7/483 , G06F7/5443
摘要： An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.
摘要翻译： 提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的装置和计算机程序产品。 改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。 进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。 此外，还使用最小数量的多路复用器来减少多路复用器延迟。
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公开(公告)号：US20080263336A1
公开(公告)日：2008-10-23
申请号：US12145482
申请日：2008-06-24
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F9/302
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译： 高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。 可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤 估计。 因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。
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24.发明授权公开(公告)号：US07392270B2
公开(公告)日：2008-06-24
申请号：US10902475
申请日：2004-07-29
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译： 本发明提供了作为多个数字的函数的移位量的计算。 至少一个解码器和至少一个加法器并联耦合。 移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。
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公开(公告)号：US20120278374A1
公开(公告)日：2012-11-01
申请号：US13544338
申请日：2012-07-09
IPC分类号： G06F11/00
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：US08219605B2
公开(公告)日：2012-07-10
申请号：US12789765
申请日：2010-05-28
IPC分类号： G06F11/00
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：US20110296229A1
公开(公告)日：2011-12-01
申请号：US12789765
申请日：2010-05-28
IPC分类号： G06F11/07
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：US20080195684A1
公开(公告)日：2008-08-14
申请号：US12105726
申请日：2008-04-18
IPC分类号： G06F7/00
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译： 本发明提供了作为多个数字的函数的移位量的计算。 至少一个解码器和至少一个加法器并联耦合。 移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。
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29.发明授权公开(公告)号：US07290023B2
公开(公告)日：2007-10-30
申请号：US10718303
申请日：2003-11-20
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/74
摘要： A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.
摘要翻译： 一个浮点单元（FPU），产生一个校正信号和一个反向的前导零信号。 指数逻辑被配置为生成指数值，第一递增指数值和第二递增指数值。 指数调整和舍入逻辑，配置为接收指数值，第一递增指数值和第二递增指数值。 指数调整和舍入逻辑还被配置为将反向引导零信号加到第一递增指数值和第二递增指数值，从而产生指数输出值，第一递增指数输出值和第二递增指数输出值 。 然后选择指数输出值，第一递增指数输出值或第二指数输出值。
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公开(公告)号：US09244654B2
公开(公告)日：2016-01-26
申请号：US13544338
申请日：2012-07-09
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点操作数，并对至少一个十进制浮点运算执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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