公开(公告)号：US20230205656A1

公开(公告)日：2023-06-29

申请号：US18175607

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

CPC classification number: G06F11/273 ,  G06F11/3636 ,  G06F11/3664 ,  G06F11/3648 ,  G06F11/348 ,  G06F11/3656 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US11231933B2

公开(公告)日：2022-01-25

申请号：US16843998

申请日：2020-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Johann Zipperer

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the execution pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.

公开(公告)号：US10929101B2

公开(公告)日：2021-02-23

申请号：US16056115

申请日：2018-08-06

Applicant: Texas Instruments Incorporated

Inventor： Christian Wiencke ,  Armin Stingl

IPC: G06F7/44 ,  G06F7/53 ,  G06F7/42

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

公开(公告)号：US20200301709A1

公开(公告)日：2020-09-24

申请号：US16843998

申请日：2020-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Johann Zipperer

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the instruction pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.

公开(公告)号：US20240012727A1

公开(公告)日：2024-01-11

申请号：US18474690

申请日：2023-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

CPC classification number: G06F11/273 ,  G06F11/3636 ,  G06F11/3664 ,  G06F11/3648 ,  G06F11/348 ,  G06F11/3656 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/26

Abstract: A processor includes execution circuitry, within an execution power domain, to process an instruction; and a debug system, within a separate debug power domain, to selectively operate to perform debugging operations on the processor. The processor further includes power control circuitry coupled to the debug system; and detection circuitry coupled to the power control circuitry. The power control circuitry causes power to be supplied to the debug system when the detection circuitry indicates that a debug tool is coupled to the processor, and disables power supply to the debug system when the detection circuitry indicates that the debug tool is not coupled to the processor.

公开(公告)号：US11150906B2

公开(公告)日：2021-10-19

申请号：US16594830

申请日：2019-10-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Shrey Bhatia

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.

公开(公告)号：US10795685B2

公开(公告)日：2020-10-06

申请号：US16378832

申请日：2019-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Markus Koesler ,  Johann Zipperer ,  Christian Wiencke ,  Wolfgang Lutsch

IPC: G06F9/38 ,  G06F11/36 ,  G06F11/267 ,  G06F9/30

Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

公开(公告)号：US20190303166A1

公开(公告)日：2019-10-03

申请号：US16378832

申请日：2019-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Markus Koesler ,  Johann Zipperer ,  Christian Wiencke ,  Wolfgang Lutsch

IPC: G06F9/38 ,  G06F11/267 ,  G06F11/36 ,  G06F9/30

Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

公开(公告)号：US10042605B2

公开(公告)日：2018-08-07

申请号：US15132280

申请日：2016-04-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Armin Stingl

IPC: G06F7/52 ,  G06F7/44 ,  G06F7/53 ,  G06F7/42

Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.