公开(公告)号：US20220206065A1

公开(公告)日：2022-06-30

申请号：US17138529

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G01R31/3177 ,  H03K3/037 ,  H03K19/003 ,  H03K5/24

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US11374576B1

公开(公告)日：2022-06-28

申请号：US17138569

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ganapat Ghotgalkar ,  Prasanth Viswanathan Pillai ,  Maheedhar Janaki Jalasutram

IPC: H03K23/00 ,  G06F1/04 ,  H03K23/58 ,  H03K21/40 ,  H03K21/38 ,  H03K23/40

Abstract: In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.

公开(公告)号：US20220103181A1

公开(公告)日：2022-03-31

申请号：US17550123

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

IPC: H03L7/087 ,  H03L7/099

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

公开(公告)号：US20200127667A1

公开(公告)日：2020-04-23

申请号：US16167440

申请日：2018-10-22

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

IPC: H03L7/087 ,  H03L7/099

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.