公开(公告)号：US11430799B2

公开(公告)日：2022-08-30

申请号：US16588090

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin Liu ,  Wei Cheng Wu ,  Yi Hsien Lu ,  Yu-Hsiung Wang ,  Juo-Li Yang

IPC: H01L27/11 ,  H01L27/11546 ,  H01L27/088 ,  H01L29/788 ,  H01L21/28 ,  H01L27/105 ,  G11C16/12 ,  G11C16/04 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11548 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US11031294B2

公开(公告)日：2021-06-08

申请号：US16102140

申请日：2018-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

公开(公告)号：US10134644B2

公开(公告)日：2018-11-20

申请号：US15782588

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/8238 ,  H01L21/266 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US09847399B1

公开(公告)日：2017-12-19

申请号：US15216565

申请日：2016-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu ,  Zhen Yang

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/28

CPC classification number: H01L29/42368 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0649

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate. The isolation region surrounds an active region of the substrate in plan view and includes an insulating material. A first dielectric layer is formed over the active region. A mask layer is formed on at least a part of a border line between the isolation region and the active region. The mask layer covers a part, but not entirety, of the first dielectric layer and a part of the isolation region surrounding the active region. The first dielectric layer not covered by the mask layer is removed such that a part of the active region is exposed. After the first dielectric layer is removed, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. A gate electrode is formed over the gate dielectric layer.

公开(公告)号：US20160225846A1

公开(公告)日：2016-08-04

申请号：US14851357

申请日：2015-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

IPC: H01L49/02 ,  H01L27/115

CPC classification number: H01L28/90 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/1157 ,  H01L27/11573 ,  H01L28/40 ,  H01L29/517 ,  H01L29/66545

Abstract: Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor.

Abstract translation: 本公开的一些实施例涉及布置在半导体衬底上的集成电路（IC），其包括闪存区域，电容器区域和逻辑区域。 电容器区域的上基板表面分别相对于闪光和逻辑区域的相应上基板表面凹陷。 一种电容器，其包括多晶硅底部电极，布置在所述多晶硅底部电极上的导电顶部电极以及分离所述底部和顶部电极的电容器电介质; 设置在电容器区域的凹陷的上基板表面上。 闪存单元设置在闪光区域的上基板表面上。 闪存单元包括具有与电容器的顶部电极的平坦化上表面共面的平坦化上表面的选择栅极。