公开(公告)号：US20190067169A1

公开(公告)日：2019-02-28

申请号：US15690283

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has chip and a redistribution layer. The redistribution layer is disposed on the chip. The redistribution layer includes joining portions having first pads and second pads surrounding the chip. The first pads are arranged around a location of the chip and the second pads are arranged over the location of the chip. The second pads located closer to the chip are narrower than the first pads located further away from the chip.

公开(公告)号：US11355418B2

公开(公告)日：2022-06-07

申请号：US16921916

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee

IPC: H01L23/42 ,  H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31

Abstract: A package structure includes a wafer-form semiconductor package and a thermal dissipating system. The wafer-form semiconductor package includes semiconductor dies electrically connected with each other. The thermal dissipating system is located on and thermally coupled to the wafer-form semiconductor package, where the thermal dissipating system has a hollow structure with a fluidic space, and the fluidic space includes a ceiling and a floor. The thermal dissipating system includes at least one inlet opening, at least one outlet opening and a plurality of first microstructures. The at least one inlet opening and the at least one outlet opening are spatially communicated with the fluidic space. The first microstructures are located on the floor, and at least one of the first microstructures is corresponding to the at least one outlet opening.

公开(公告)号：US11328975B2

公开(公告)日：2022-05-10

申请号：US16942750

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee ,  Po-Fan Lin

IPC: H01L23/36 ,  H01L23/04 ,  H05K7/20

Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.

公开(公告)号：US11031344B2

公开(公告)日：2021-06-08

申请号：US16114246

申请日：2018-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

Abstract: Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.

公开(公告)号：US20210159201A1

公开(公告)日：2021-05-27

申请号：US16935175

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee ,  Po-Fan Lin

IPC: H01L23/00 ,  H01L23/48

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

公开(公告)号：US20210066279A1

公开(公告)日：2021-03-04

申请号：US16888874

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee ,  Liang-Ju Yen

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/00

Abstract: One of semiconductor packages includes a substrate and a package structure. The package structure is bonded to the substrate and includes a first redistribution layer structure, a first logic die, a plurality of second logic dies, a first memory die, a first heat conduction block and a first encapsulant. The first logic die and the second logic dies are disposed over and electrically connected to the first redistribution layer structure. The first memory die is disposed over the first logic die and the second logic dies and electrically connected to first redistribution layer structure. The first heat conduction block is disposed over the first logic die and the second logic dies. The first encapsulant encapsulates the first memory die and the first heat conduction block.

公开(公告)号：US20200075496A1

公开(公告)日：2020-03-05

申请号：US16114246

申请日：2018-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00

Abstract: Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.

公开(公告)号：US20200020643A1

公开(公告)日：2020-01-16

申请号：US16035711

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: Semiconductor packages and methods of forming the same are provided. a semiconductor package includes a sub-package, a second die and a second molding layer. The sub-package includes a first die, a first molding layer aside the first die and a first redistribution layer structure disposed over the first die and the first molding layer and electrically connected to the first die. The second die is disposed over the sub-package, wherein the first die and the second die are disposed on opposite surfaces of the first redistribution layer structure. The second molding layer encapsulates the sub-package and the second die.

公开(公告)号：US20190385989A1

公开(公告)日：2019-12-19

申请号：US16009209

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chun-Hui Yu

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a first semiconductor die, a plurality of conductive pins, an insulating encapsulant, a backside connection structure and a redistribution layer. The conductive pins are surrounding the first semiconductor die and have a base portion with a first width and a body portion with a second width, the base portion is connected to the body portion and the first width being larger than the second width. The insulating encapsulant is encapsulating the first semiconductor die and the conductive pins. The backside connection structure is disposed on the first semiconductor die and electrically connected to the conductive pins. The redistribution layer is disposed on the first semiconductor die, and electrically connected to the first semiconductor die and the conductive pins. The second package is stacked on the first package and electrically connected to the backside connection structure.

公开(公告)号：US10510695B2

公开(公告)日：2019-12-17

申请号：US16219981

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Kuo-Chung Yee

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via.