公开(公告)号：US11088059B2

公开(公告)日：2021-08-10

申请号：US16441020

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Jiun-Yi Wu ,  Shou-Yi Wang

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

Abstract: A package structure, a RDL structure and method of forming the same are provided. The package structure includes a die structure, a RDL structure and a conductive terminal. The RDL structure is electrically connected to the die structure. The conductive terminal is electrically connected to the die structure through the RDL structure. The RDL structure includes a first redistribution layer and a second redistribution layer over the first redistribution layer. The first redistribution layer includes a ground plate. The second redistribution layer includes a signal line, and the signal line includes a signal via and a signal trace, the signal trace is electrically connected to the first redistribution layer through the signal via, and an overlapping area between the signal trace and the ground plate in a direction perpendicular to a bottom surface of the signal trace is less than an area of the bottom surface of the signal trace.

公开(公告)号：US20210202266A1

公开(公告)日：2021-07-01

申请号：US16869066

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.