公开(公告)号：US20220013463A1

公开(公告)日：2022-01-13

申请号：US16924130

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Yen-Ping Wang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

公开(公告)号：US20200373173A1

公开(公告)日：2020-11-26

申请号：US16991010

申请日：2020-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.

公开(公告)号：US10748861B2

公开(公告)日：2020-08-18

申请号：US15980764

申请日：2018-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L25/11 ,  H01L25/10 ,  H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation.

公开(公告)号：US10276404B2

公开(公告)日：2019-04-30

申请号：US15690300

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chung-Hao Tsai ,  Chun-Lin Lu ,  Yen-Ping Wang ,  Che-Wei Hsu

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/768

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and a second redistribution structure. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The second redistribution structure is disposed on the die and the insulation encapsulation. At least one of the first redistribution structure and the second redistribution structure includes a dielectric layer, a feed line, and a signal enhancement layer. The feed line is at least partially disposed on the dielectric layer. The signal enhancement layer covers the feed line. The signal enhancement layer has a lower dissipation factor (Df) and/or a lower permittivity (Dk) than the dielectric layer.

公开(公告)号：US11417616B2

公开(公告)日：2022-08-16

申请号：US16924116

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.

公开(公告)号：US11348874B2

公开(公告)日：2022-05-31

申请号：US16924130

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Yen-Ping Wang

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

公开(公告)号：US11515173B2

公开(公告)日：2022-11-29

申请号：US16869066

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20210391230A1

公开(公告)日：2021-12-16

申请号：US17462115

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang

IPC: H01L23/24 ,  H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

公开(公告)号：US20210202266A1

公开(公告)日：2021-07-01

申请号：US16869066

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US20190355679A1

公开(公告)日：2019-11-21

申请号：US15980764

申请日：2018-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation.