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公开(公告)号：US09143187B2
公开(公告)日：2015-09-22
申请号：US14264708
申请日：2014-04-29
发明人： June Chul Roh , Anuj Batra , Sudipto Chakraborty , Srinath Hosur
IPC分类号： H04B1/00 , H04B1/69 , H04B1/7176
CPC分类号： H04B1/69 , H04B1/7176 , H04B2001/6908
摘要： A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.
摘要翻译： 本文公开了适用于体区网络的符号调制系统。 符号调制系统包括符号映射器。 符号映射器被配置为确定符号的传输代表将发生的预定符号传输间隔内的时间。 该时间基于符号的值和跳时序列的值来确定。 该时间是从基于多个符号值的时隙中选出的，以及在每个基于符号值的时隙内的多个跳时序列子时隙。 符号映射器被配置为在符号传输间隔内产生单个保护间隔。 单个保护间隔定位成终止符号传输间隔。
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公开(公告)号：US20140064336A1
公开(公告)日：2014-03-06
申请号：US14074448
申请日：2013-11-07
发明人： June Chul Roh , Anuj Batra , Sudipto Chakraborty , Srinath Hosur
IPC分类号： H04B1/69
CPC分类号： H04B1/69 , H04B1/7176 , H04B2001/6908
摘要： A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.
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公开(公告)号：US11728836B2
公开(公告)日：2023-08-15
申请号：US17739316
申请日：2022-05-09
CPC分类号： H04B1/06 , H04L27/06 , H04W52/0229 , H04W52/0254 , Y02D30/70
摘要： A wireless wake-up receiver includes multiple signal chains each signal chain being coupled to continuously receive a signal from a respective antenna and to provide a respective detected pattern at a signal chain output. Each signal chain includes a first path having a mixer-first architecture and operates in a bandpass-mode using differential signals. The wireless wake-up receiver also includes a digital correlator operable to receive the respective detected patterns and to determine whether one of the respective detected patterns is equal to a desired pattern.
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公开(公告)号：US11705863B2
公开(公告)日：2023-07-18
申请号：US17573662
申请日：2022-01-12
发明人： Sudipto Chakraborty
IPC分类号： H03F3/213 , H03F3/24 , H03G3/30 , H03B5/12 , H03G1/00 , H03F3/21 , H03F3/45 , H03F1/02 , H03G3/00 , H04B1/04
CPC分类号： H03B5/1212 , H03B5/1228 , H03B5/1265 , H03F1/0211 , H03F1/0277 , H03F3/211 , H03F3/213 , H03F3/245 , H03F3/45 , H03G1/0005 , H03G3/004 , H03G3/3042 , H04B2001/0416
摘要： An integrated circuit includes an oscillator and a power amplifier. The oscillator includes a first node, a second node, and a network of one or more reactive components coupled between the first node and the second node. The power amplifier includes a first input coupled to the first output of the oscillator, a second input coupled to the second output of the oscillator, and an output. The power amplifier includes a coarse gain control circuit, a first amplifier stage, and a second amplifier stage.
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公开(公告)号：US11258404B2
公开(公告)日：2022-02-22
申请号：US17034099
申请日：2020-09-28
发明人： Sudipto Chakraborty
IPC分类号： H03F3/213 , H03F3/24 , H03B5/12 , H03G1/00 , H03G3/30 , H03F3/21 , H03F3/45 , H03F1/02 , H04B1/04
摘要： A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.
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公开(公告)号：US10856225B2
公开(公告)日：2020-12-01
申请号：US16120154
申请日：2018-08-31
摘要： A system of multiple concurrent receivers is described to process multiple narrow bandwidth wireless signals with arbitrary bandwidth and center frequency separation. These multiple receivers may provide a downconverted signal at the baseband frequency to process signal bandwidth using the lowest power consumption while using fully modular signal processing blocks operating at the low frequency. The concurrent receivers may operate from a single high frequency amplifier and may be derived from a low impedance point to reduce loading and improve scalability. The center frequency and bandwidth of each of the channels as well as phases of each of the channels may be independently reconfigured to achieve scalability, and on-chip test and calibration capability.
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公开(公告)号：US10574278B2
公开(公告)日：2020-02-25
申请号：US15350094
申请日：2016-11-13
摘要： A wireless wake-up receiver includes multiple signal chains each signal chain being coupled to continuously receive a signal from a respective antenna and to provide a respective detected pattern at a signal chain output. Each signal chain includes a first path having a mixer-first architecture and operates in a bandpass-mode using differential signals. The wireless wake-up receiver also includes a digital correlator operable to receive the respective detected patterns and to determine whether one of the respective detected patterns is equal to a desired pattern.
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公开(公告)号：US10530402B2
公开(公告)日：2020-01-07
申请号：US16380582
申请日：2019-04-10
发明人： Sudipto Chakraborty
摘要： A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the outputs, leaving no further scope of nonlinearity in the signal chain.
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公开(公告)号：US20190305808A1
公开(公告)日：2019-10-03
申请号：US16380582
申请日：2019-04-10
发明人： Sudipto Chakraborty
摘要： A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the outputs, leaving no further scope of nonlinearity in the signal chain.
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公开(公告)号：US10291270B2
公开(公告)日：2019-05-14
申请号：US16148891
申请日：2018-10-01
发明人： Sudipto Chakraborty
摘要： A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the output, leaving no further scope of nonlinearity in the signal chain.
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