VARIABLE GAIN POWER AMPLIFIERS
    1.
    发明申请

    公开(公告)号:US20210013833A1

    公开(公告)日:2021-01-14

    申请号:US17034099

    申请日:2020-09-28

    摘要: A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.

    Wideband Low Distortion Power Amplifier
    2.
    发明申请

    公开(公告)号:US20190036558A1

    公开(公告)日:2019-01-31

    申请号:US16148891

    申请日:2018-10-01

    IPC分类号: H04B1/04 H03F3/24

    摘要: A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the output, leaving no further scope of nonlinearity in the signal chain.

    VARIABLE GAIN POWER AMPLIFIERS
    3.
    发明申请

    公开(公告)号:US20170288796A1

    公开(公告)日:2017-10-05

    申请号:US15627249

    申请日:2017-06-19

    摘要: A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.

    Low power harmonic wake up radio
    4.
    发明授权

    公开(公告)号:US09743354B2

    公开(公告)日:2017-08-22

    申请号:US14588629

    申请日:2015-01-02

    IPC分类号: H04W52/02

    CPC分类号: H04W52/0229 Y02D70/00

    摘要: A wireless receiver includes a receiver mixer having at least two sets of switches connected to selectively pass a portion of a received RF signal to the mixer's output. Different sets of the switches are activated by different phases of a local oscillator to effect passing of different phases of the RF signal to the output. These outputs are combined in various ways to obtain operation of the main receiver and the wake up receiver modes at harmonically related carrier frequencies with as low as possible subharmonic multi-phase clock generation network. This can be used to detect a wake up signal with a very fast response time, minimal area overhead, minimal power usage, and equal loading to the local oscillator network providing the phases to the mixer to maintain excellent phase balance and precise harmonic selectivity.

    SoC transceiver with single ended/differential modes, tunable capacitor and latch
    8.
    发明授权
    SoC transceiver with single ended/differential modes, tunable capacitor and latch 有权
    具有单端/差分模式的SoC收发器,可调谐电容器和锁存器

    公开(公告)号:US09331734B2

    公开(公告)日:2016-05-03

    申请号:US14740961

    申请日:2015-06-16

    摘要: A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.

    摘要翻译: 芯片上的系统(SoC)包括收发器,其包括发射器和接收器,其中发射器和接收器中的至少一个具有可配置部分,其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线,其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线,其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。