公开(公告)号：US10168992B1

公开(公告)日：2019-01-01

申请号：US15671679

申请日：2017-08-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F7/544 ,  G06F7/483

Abstract: Processor architectures and associated methods provide interruptible, instruction-based trigonometric function computation based on CORDIC iterations, receiving and outputting floating-point values (e.g., 64-bit). The architectures and methods can provide multiple CORDIC-like iterations in as little as a single CPU processing cycle to provide an overall faster execution of trigonometric operations while having zero additional overhead for service of time-critical interrupts. Post interrupt service, a CORDIC operation can be resumed from where it was interrupted.

公开(公告)号：US20170149418A1

公开(公告)日：2017-05-25

申请号：US15274576

申请日：2016-09-23

Applicant: Texas Instruments Incorporated

Inventor： Alexander Tessarolo ,  Saya Goud Langadi

IPC: H03K3/03 ,  H03K5/159 ,  H03K19/20

CPC classification number: H03K3/0315 ,  G01R23/02 ,  H03K5/159 ,  H03K19/20

Abstract: A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The oscillator delay line includes N timing delay elements sequentially coupled in a ring to generate a first clock signal. The first and second capture delay lines each include M capture delay elements sequentially coupled to pass a received signal in a first direction along a first signal path and to pass a clock signal in a second direction opposite to the first direction along a second signal path. The first capture delay line uses the first clock signal and the second capture delay line uses an inverse of the first clock signal. Each capture delay element forms a flip-flop and provides a one-bit output. All delay elements have essentially identical timing and M is equal to either N or to N/2.

公开(公告)号：US20250060965A1

公开(公告)日：2025-02-20

申请号：US18427411

申请日：2024-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander Tessarolo ,  Venkatesh Natarajan ,  Alan Davis

IPC: G06F9/38 ,  G06F9/30

Abstract: Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions and cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

公开(公告)号：US20250045052A1

公开(公告)日：2025-02-06

申请号：US18587432

申请日：2024-02-26

Applicant: Texas Instruments Incorporated

Inventor： Venkatesh Natarajan ,  Saya Goud Langadi ,  Alexander Tessarolo

IPC: G06F9/30 ,  G06F9/38

Abstract: An example apparatus includes: address generation circuitry configured to generate a first address associated with a first packet, a second address associated with a second packet, and a third address associated with a third packet, wherein: the first packet includes a branch instruction; the branch instruction includes a first field that specifies a branch target, and a second field that is different from the first field; and the third packet includes the branch target of the branch instruction; buffer circuitry configured to receive the first packet, the second packet, and the third packet; decoder circuitry coupled to the buffer circuitry, the decoder circuitry configured to decode the first packet, the second packet, and the third packet; discontinuity controller circuitry coupled to the buffer circuitry and the decoder circuitry and configured to determine whether to cause the address generation circuitry to generate the second address.

公开(公告)号：US20230221959A1

公开(公告)日：2023-07-13

申请号：US18174715

申请日：2023-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/30152 ,  G06F9/4843 ,  G06F9/3851

Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

公开(公告)号：US11593110B2

公开(公告)日：2023-02-28

申请号：US17143989

申请日：2021-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

公开(公告)号：US10725742B2

公开(公告)日：2020-07-28

申请号：US16000736

申请日：2018-06-05

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Richard Mark Poley ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F7/548

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

公开(公告)号：US10359995B2

公开(公告)日：2019-07-23

申请号：US15142047

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander Tessarolo ,  Prasanth Viswanathan Pillai ,  Venkatesh Natarajan

IPC: G06F7/535

Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

公开(公告)号：US09614704B2

公开(公告)日：2017-04-04

申请号：US15083549

申请日：2016-03-29

Applicant: Texas Instruments Incorporated

Inventor： Venkatesh Natarajan ,  Alexander Tessarolo

IPC: H04L25/49 ,  H04L1/00 ,  H04L5/00

CPC classification number: H04L25/49 ,  G06F13/4282 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/0083 ,  H04L1/009 ,  H04L1/0091 ,  H04L5/0044 ,  H04L25/0266

Abstract: Methods and apparatus to perform serial communications are disclosed. An example serial data transmitter includes: a clock signal generator to generate a digital clock signal; a clock signal controller to enable the clock signal generator; a line break signal generator to, in response to an expiration of a time period, trigger the transmission of a transmission line check frame; a data integrity check generator to generate error detection data corresponding to first data to be transmitted via the transmission port; a signal framer to: generate a first data frame having a preamble, second data, third data, the first data, the error detection data, and fourth data; and generate the transmission line check frame.