公开(公告)号：US06627500B1

公开(公告)日：2003-09-30

申请号：US10064796

申请日：2002-08-19

申请人： Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/978

摘要： A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.

摘要翻译： 一种制造氮化物只读存储器的方法。 在衬底上形成包括绝缘层，电荷陷阱层和绝缘层的俘获电介质夹层结构。 在绝缘层中形成具有凹入侧壁的开口。 形成热氧化物层以填充开口，使得凹入的侧壁被完全密封。 因此，电荷陷阱层被绝缘层和热氧化物层密封，以避免控制栅极和电荷陷阱层之间的直接接触，从而防止数据丢失。

公开(公告)号：US06580630B1

公开(公告)日：2003-06-17

申请号：US10165715

申请日：2002-06-07

申请人： Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan

发明人： Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan

IPC分类号： G11C1300

CPC分类号： H01L29/66833 ,  G11C16/18 ,  H01L21/28282 ,  H01L29/792

摘要： The presents invention provides an initialization method of a P-type silicon nitride read only memory. A P-type silicon nitride read only memory is provided. An ultra-violet light is uniformly radiated onto the P-type silicon nitride read only memory. Electron traps are thus evenly distributed in a silicon nitride layer of the P-type silicon nitride read only memory. The P-type silicon nitride read only memory is thus uniformly programmed to a low threshold voltage (Low|Vt|) to achieve the device initialization effect.

摘要翻译： 本发明提供了一种P型氮化硅只读存储器的初始化方法。 提供了P型氮化硅只读存储器。 紫外光均匀地辐射到P型氮化硅只读存储器上。 因此，电子俘获器均匀分布在P型氮化硅只读存储器的氮化硅层中。 因此，P型氮化硅只读存储器被均匀地编程到低阈值电压（Low | Vt |）以实现器件初始化效果。

公开(公告)号：US06413815B1

公开(公告)日：2002-07-02

申请号：US09682069

申请日：2001-07-17

申请人： Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

发明人： Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

IPC分类号： H01L218242

CPC分类号： H01L21/76808 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of simultaneously forming a dual damascence runner and a metal-insulator-metal (MIM) capacitor on a semiconductor wafer. The semiconductor wafer has a first dielectric layer, which has at least a first conductive layer and at least a bottom electrode of the MIM capacitor. The surfaces of the first conductive layer and the bottom electrode of the MIM capacitor are covered with a barrier layer. A second dielectric layer, a stop layer and a third dielectric layer are formed on the surface of the barrier layer and form a sandwiched structure. A first photoresist layer is formed and the third dielectric layer is anisotropically etched down to the stop layer, thus forming a trench and an opening in the third dielectric layer above the conductive layer and the bottom electrode of the MIM capacitor. A second photoresist layer is formed and the stop layer and the second dielectric layer are etched at a bottom of the opening down to the surface of the barrier layer so as to form an opening of the top electrode. A third photoresist layer is formed and the stop layer, the second dielectric layer and the barrier layer are etched through the contact opening down to the surface of the first conductive layer so as to form a contact hole.

摘要翻译： 一种在半导体晶片上同时形成双重阻力流道和金属 - 绝缘体 - 金属（MIM）电容器的方法。 半导体晶片具有至少具有MIM电容器的第一导电层和至少底部电极的第一电介质层。 MIM电容器的第一导电层和底部电极的表面被阻挡层覆盖。 在阻挡层的表面上形成第二电介质层，阻挡层和第三电介质层，并形成夹层结构。 形成第一光致抗蚀剂层，并且将第三介电层各向异性地向下蚀刻到停止层，从而在MIM电容器的导电层和底部电极上方的第三介电层中形成沟槽和开口。 形成第二光致抗蚀剂层，并且将阻止层和第二介电层在开口的底部蚀刻到阻挡层的表面，以形成顶部电极的开口。 形成第三光致抗蚀剂层，并且通过接触开口将停止层，第二介电层和阻挡层蚀刻到第一导电层的表面，以形成接触孔。

公开(公告)号：US06444519B1

公开(公告)日：2002-09-03

申请号：US10120286

申请日：2002-04-09

申请人： Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan

发明人： Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L21/26533 ,  H01L21/32105

摘要： The invention provides a method for forming a capacitor in a mixed mode circuit device through ion implantation. The method includes forming a polysilicon layer over a substrate, which substrate has isolation region formed thereon. An ion implantation process is performed to implant oxygen ions into the polysilicon layer. An annealing process is performed to trigger an reaction between the oxygen ions and the silicon ions. As a result, a silicon oxide layer is formed within the polysilicon layer. The silicon layer and the polysilicon layer are patterned, where the top portion of the polysilicon layer above the silicon oxide layer serves as an upper electrode of a capacitor. The polysilicon layer below the silicon oxide layer serves as the lower electrode.

摘要翻译： 本发明提供了一种通过离子注入在混合模式电路器件中形成电容器的方法。 该方法包括在衬底上形成多晶硅层，该衬底上形成有隔离区。 执行离子注入工艺以将氧离子注入到多晶硅层中。 执行退火处理以触发氧离子和硅离子之间的反应。 结果，在多晶硅层内形成氧化硅层。 图案化硅层和多晶硅层，其中氧化硅层上方的多晶硅层的顶部用作电容器的上电极。 氧化硅层下面的多晶硅层用作下电极。

公开(公告)号：US20050277250A1

公开(公告)日：2005-12-15

申请号：US10865401

申请日：2004-06-10

申请人： Shyi-Shuh Pan ,  Chong-Jen Huang

发明人： Shyi-Shuh Pan ,  Chong-Jen Huang

IPC分类号： H01L21/336 ,  H01L21/469 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/7923

摘要： Roughly described, a device having twin bit floating gate memory cells is fabricated by first providing a substrate having formed thereon, within a memory area, a composite charge storage film and a protective liner layer over the composite film. The memory area further includes oxide features over buried diffusion regions in the substrate, and polysilicon spacers over the composite film against the sidewalls of the oxide features. The method further involves etching an isolation trench through the composite film laterally between two of the oxide features, using the polysilicon spacers as a mask, and forming an insulator in the trench. A gate conductor is then formed overlying both the composite film and the filled isolation trench between the two oxide features.

摘要翻译： 粗略地描述，具有双位浮动栅极存储单元的器件通过首先在存储区域内形成的衬底，复合电荷存储膜和复合膜上的保护衬垫层来制造。 存储区域还包括在衬底中的掩埋扩散区域上的氧化物特征，以及抵靠氧化物特征侧壁的复合膜上的多晶硅间隔物。 该方法还包括使用多晶硅间隔物作为掩模，在两个氧化物特征之间侧向蚀刻通过复合膜的隔离沟槽，并在沟槽中形成绝缘体。 然后在两个氧化物特征之间形成覆盖复合膜和填充隔离沟槽的栅极导体。

公开(公告)号：US06972230B1

公开(公告)日：2005-12-06

申请号：US10865401

申请日：2004-06-10

申请人： Shyi-Shuh Pan ,  Chong-Jen Huang

发明人： Shyi-Shuh Pan ,  Chong-Jen Huang

IPC分类号： H01L21/336 ,  H01L21/469 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/7923

摘要： Roughly described, a device having twin bit floating gate memory cells is fabricated by first providing a substrate having formed thereon, within a memory area, a composite charge storage film and a protective liner layer over the composite film. The memory area further includes oxide features over buried diffusion regions in the substrate, and polysilicon spacers over the composite film against the sidewalls of the oxide features. The method further involves etching an isolation trench through the composite film laterally between two of the oxide features, using the polysilicon spacers as a mask, and forming an insulator in the trench. A gate conductor is then formed overlying both the composite film and the filled isolation trench between the two oxide features.

摘要翻译： 粗略地描述，具有双位浮动栅极存储单元的器件通过首先在存储区域内形成的衬底，复合电荷存储膜和复合膜上的保护衬垫层来制造。 存储区域还包括在衬底中的掩埋扩散区域上的氧化物特征，以及抵靠氧化物特征侧壁的复合膜上的多晶硅间隔物。 该方法还包括使用多晶硅间隔物作为掩模，在两个氧化物特征之间侧向蚀刻通过复合膜的隔离沟槽，并在沟槽中形成绝缘体。 然后在两个氧化物特征之间形成覆盖复合膜和填充隔离沟槽的栅极导体。