公开(公告)号：US06440798B1

公开(公告)日：2002-08-27

申请号：US09682148

申请日：2001-07-26

申请人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan ,  Ying-Tso Chen

发明人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Shyi-Shuh Pan ,  Ying-Tso Chen

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： The present invention gives a method for creating a NROM memory from a semiconductor substrate. Numerous process steps are included to achieve this including forming shallow trench isolation areas, many ion implantation processes, ROM code implantation processes, photolithography and creation of layers and removal of layers. At the end of the process a mixed-signal circuit embedded NROM and NROM memory are created.

摘要翻译： 本发明提供了一种从半导体衬底生成NROM存储器的方法。 包括许多工艺步骤以实现这一点，包括形成浅沟槽隔离区域，许多离子注入工艺，ROM代码注入工艺，光刻以及层的创建和层的去除。 在该过程结束时，创建了嵌入NROM和NROM存储器的混合信号电路。

公开(公告)号：US06448126B1

公开(公告)日：2002-09-10

申请号：US09682217

申请日：2001-08-07

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823412

摘要： A method of forming an embedded memory integrating nitride read only memory starts by forming an ONO layer and a protective cap layer on a surface of a semiconductor substrate defined with a memory area and a periphery area. The periphery area has a first, a second and a third device area. An etching and a first ion implantation process form each bit line in the memory area. A spacer is then formed at either side of the protective cap layer and the ONO layer in the memory area, and the protective cap layer and the ONO layer are removed in the first device area. The threshold voltage for the first device area is adjusted and a first thermal oxidation process forms a buried drain oxide layer atop each bit line and a first gate oxide layer on the surface of the first device area, respectively. The protective cap layer and the ONO layer are removed from the second device area and the third device area, and a second gate oxide layer is formed in the second device area and the third device area. Finally, the protective cap layer in the memory area and the second gate oxide layer in the third device area are removed, and a third gate oxide layer is formed in the third device area.

摘要翻译： 集成氮化物只读存储器的嵌入式存储器的形成方法首先通过在由存储区域和周边区域限定的半导体衬底的表面上形成ONO层和保护覆盖层。 周边区域具有第一，第二和第三设备区域。 蚀刻和第一离子注入工艺在存储区域中形成每个位线。 然后在保护盖层和存储区域中的ONO层的任一侧形成间隔物，并且在第一装置区域中去除保护盖层和ONO层。 调整第一器件区域的阈值电压，第一热氧化工艺分别在第一器件区域的表面上的每个位线和第一栅极氧化物层的顶部形成掩埋的漏极氧化物层。 从第二设备区域和第三设备区域去除保护盖层和ONO层，并且在第二设备区域和第三设备区域中形成第二栅极氧化物层。 最后，去除存储区域中的保护盖层和第三器件区域中的第二栅极氧化物层，并且在第三器件区域中形成第三栅极氧化物层。

公开(公告)号：US06413815B1

公开(公告)日：2002-07-02

申请号：US09682069

申请日：2001-07-17

申请人： Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

发明人： Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

IPC分类号： H01L218242

CPC分类号： H01L21/76808 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of simultaneously forming a dual damascence runner and a metal-insulator-metal (MIM) capacitor on a semiconductor wafer. The semiconductor wafer has a first dielectric layer, which has at least a first conductive layer and at least a bottom electrode of the MIM capacitor. The surfaces of the first conductive layer and the bottom electrode of the MIM capacitor are covered with a barrier layer. A second dielectric layer, a stop layer and a third dielectric layer are formed on the surface of the barrier layer and form a sandwiched structure. A first photoresist layer is formed and the third dielectric layer is anisotropically etched down to the stop layer, thus forming a trench and an opening in the third dielectric layer above the conductive layer and the bottom electrode of the MIM capacitor. A second photoresist layer is formed and the stop layer and the second dielectric layer are etched at a bottom of the opening down to the surface of the barrier layer so as to form an opening of the top electrode. A third photoresist layer is formed and the stop layer, the second dielectric layer and the barrier layer are etched through the contact opening down to the surface of the first conductive layer so as to form a contact hole.

摘要翻译： 一种在半导体晶片上同时形成双重阻力流道和金属 - 绝缘体 - 金属（MIM）电容器的方法。 半导体晶片具有至少具有MIM电容器的第一导电层和至少底部电极的第一电介质层。 MIM电容器的第一导电层和底部电极的表面被阻挡层覆盖。 在阻挡层的表面上形成第二电介质层，阻挡层和第三电介质层，并形成夹层结构。 形成第一光致抗蚀剂层，并且将第三介电层各向异性地向下蚀刻到停止层，从而在MIM电容器的导电层和底部电极上方的第三介电层中形成沟槽和开口。 形成第二光致抗蚀剂层，并且将阻止层和第二介电层在开口的底部蚀刻到阻挡层的表面，以形成顶部电极的开口。 形成第三光致抗蚀剂层，并且通过接触开口将停止层，第二介电层和阻挡层蚀刻到第一导电层的表面，以形成接触孔。

公开(公告)号：US06448137B1

公开(公告)日：2002-09-10

申请号：US09682941

申请日：2001-11-02

申请人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang ,  Ying-Tso Chen

发明人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang ,  Ying-Tso Chen

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11573 ,  Y10S438/981

摘要： A method of forming an NROM comprising mixed-signal circuits is provided. The method starts by providing a semiconductor substrate having a memory area and a periphery area. The periphery area has a plurality of active areas isolated by an isolation layer. A bottom electrode of a capacitor is formed atop the isolation layer in the periphery area. An ONO(oxide-nitride-oxide) process is performed. A photolithography, an anisotropic etching, and an ion implantation process are performed in order to etch the ONO dielectric layer in a bit line region not protected by the first photolithography process, and to form a plurality of buried bit lines. A photolithography and an ion implantation process are performed in order to form at least one ion well. The surface of the active area in the periphery area is wet etched. An oxidation process is performed in order to simultaneously form at least one gate oxide layer with a specific thickness in the active area, and to form a thermal oxide layer atop each of the buried bit lines in the memory area. Each of the gates, the top electrode of the capacitor and the resistor are formed in the periphery area, and a word line is formed in the memory area.

摘要翻译： 提供了一种形成包括混合信号电路的NROM的方法。 该方法通过提供具有存储区域和周边区域的半导体衬底开始。 周边区域具有由隔离层隔离的多个有效区域。 电容器的底部电极形成在外围区域中的隔离层顶部。 进行ONO（氧化物 - 氮化物 - 氧化物）处理。 执行光刻，各向异性蚀刻和离子注入工艺以蚀刻未被第一光刻工艺保护的位线区域中的ONO介电层，并形成多个掩埋位线。 进行光刻和离子注入工艺以形成至少一个离子阱。 周边区域的有源区域的表面被湿蚀刻。 执行氧化处理以在有源区域中同时形成具有特定厚度的至少一个栅极氧化物层，并且在存储区域中的每个掩埋位线上形成热氧化物层。 每个栅极，电容器的顶部电极和电阻器形成在周边区域中，并且在存储区域中形成字线。

公开(公告)号：US06432778B1

公开(公告)日：2002-08-13

申请号：US09682216

申请日：2001-08-07

申请人： Erh-Kun Lai ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

发明人： Erh-Kun Lai ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC分类号： H01L218236

CPC分类号： H01L27/11266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11293 ,  H01L27/11573 ,  Y10S438/954

摘要： An ONO dielectric layer is formed on the surface of a substrate, and then a plurality of bit lines are formed in the substrate by utilizing a photolithography and an ion implantation process. Thereafter the ONO dielectric layer in the periphery area is removed and the threshold voltage of the periphery transistor is adjusted. After the ONO dielectric layer in the read only memory area is removed, and a buried drain oxide layer and a plurality of gate oxide layers are formed atop each bit line and the surface of each device respectively. Then each word line in the memory area and each gate of each periphery transistor in the periphery area is formed so as to simultaneously form at least a nitride read only memory in the nitride read only memory area and a high, low threshold voltage device in the read only memory area. Finally the threshold voltage of the high threshold voltage device is adjusted by utilizing a ROM code implantation process.

摘要翻译： 在衬底的表面上形成ONO电介质层，然后利用光刻和离子注入工艺在衬底中形成多个位线。 此后，去除外围区域中的ONO电介质层，并调整周边晶体管的阈值电压。 在只读存储器区域中的ONO介电层被去除之后，并且在每个位线和每个器件的表面上分别形成掩埋的漏极氧化物层和多个栅极氧化物层。 然后形成周边区域的存储区域和每个周边晶体管的每个栅极的每个字线，以便在氮化物只读存储器区域和高，低阈值电压器件中同时形成至少一个氮化物只读存储器 只读存储区。 最后，通过利用ROM代码注入过程来调整高阈值电压器件的阈值电压。

公开(公告)号：US06723603B2

公开(公告)日：2004-04-20

申请号：US10183530

申请日：2002-06-28

申请人： Chien-Hung Liu ,  Erh-Kun Lai ,  Shyi Shuh Pan ,  Shou Wei Huang ,  Ying Tzoo Chen

发明人： Chien-Hung Liu ,  Erh-Kun Lai ,  Shyi Shuh Pan ,  Shou Wei Huang ,  Ying Tzoo Chen

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7887

摘要： The present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell. In the present invention, recessed poly-Si spacers are used to fabricate discontinuous floating gates below a control gate to build a flash memory with 2bit/cell. The present invention is characterized in that the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process. Moreover, each memory cell in this flash memory can store two bits, hence increasing the memory capacity.

摘要翻译： 本发明提供了利用多晶硅间隔物的制造工艺来构建具有2bit / cell的闪速存储器的方法。 在本发明中，凹入的多晶硅间隔物用于制造控制栅极下面的不连续的浮动栅极以构建具有2bit / cell的闪速存储器。 本发明的特征在于，多晶硅间隔物的制造工艺被利用以完全以自动对准方式完成浮栅的制造工艺，而无需任何额外的掩模工艺。 此外，该闪速存储器中的每个存储单元可以存储两个位，从而增加存储器容量。

公开(公告)号：US06551880B1

公开(公告)日：2003-04-22

申请号：US10146876

申请日：2002-05-17

申请人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shou Wei Huang ,  Shyi-Shuh Pan ,  Ying Tzoo Chen

发明人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shou Wei Huang ,  Shyi-Shuh Pan ,  Ying Tzoo Chen

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

摘要： The present invention discloses a method of utilizing the fabrication process of floating gate spacer to build a twin-bit MONOS/SONOS memory, wherein recessed ONO spacers are used to fabricate a discontinuous floating gate below a poly control gate to obtain a MONOS/SONOS memory device having twinbit memory cells. Cross talk between charges stored in the two bits can be avoided, hence enhancing the reliability of memory device. Moreover, if the voltage Vt varies during the fabrication process, the device can restore its normal characteristics through the individual and separate characteristic of the two bits and by using program or erase condition. The present invention can utilize the fabrication process of ONO spacer to complete the fabrication process of floating gate in automatic alignment way without the need of undergoing several mask processes.

摘要翻译： 本发明公开了利用浮栅间隔器的制造工艺来构建双位MONOS / SONOS存储器的方法，其中使用凹入的ONO间隔物来制造多控制栅极下的不连续浮动栅极，以获得MONOS / SONOS存储器 具有双位存储单元的器件。 可以避免存储在两位中的电荷之间的串扰，从而提高存储器件的可靠性。 此外，如果在制造过程中电压Vt变化，则器件可以通过两位的单独和分离的特性以及使用编程或擦除条件恢复其正常特性。 本发明可以利用ONO间隔物的制造工艺以自动对准的方式完成浮栅的制造工艺，而不需要经历多次掩模工艺。

公开(公告)号：US06548406B2

公开(公告)日：2003-04-15

申请号：US09930998

申请日：2001-08-17

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L21302

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L29/66833

摘要： A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

摘要翻译： 公开了一种形成具有金属氧化物氮化物半导体（MONOS）存储器和混合信号电路的集成电路的方法。 本发明将诸如MONOS器件的非易失性存储器件和诸如MOS器件的逻辑器件以及PIP电容器集成到具有减少的工艺步骤的SOC器件中。

公开(公告)号：US06383903B1

公开(公告)日：2002-05-07

申请号：US09918638

申请日：2001-08-01

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L213205

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/1052

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氧化物层作为掩模层，在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06482738B1

公开(公告)日：2002-11-19

申请号：US09996821

申请日：2001-11-30

申请人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Ying-Tso Chen ,  Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/115 ,  H01L29/665 ,  H01L29/6656

摘要： The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of present invention achieve above objectives by principally using a design rule to adequately arrange elements in proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is previously formed in the spaced region between the two neighboring memory cells and is used as a mask. Thus, in a following selective etching process, a part of silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objectives is achieved.

摘要翻译： 本发明主要提供一种在积分电路上局部形成金属硅化物的方法，并且避免由同一字线上的存储单元之间形成的金属硅化物引起的漏电流的现象。 本发明的方法通过主要使用设计规则来适当地排列适当距离的元件来达到上述目的。 在一个实施例中，为了在积分电路上形成金属硅化物层并且避免在相同字线上的两个相邻存储器单元之间形成的金属硅化物，预先在两个相邻存储器单元之间的间隔区域中形成电介质层，并且是 用作面具。 因此，在随后的选择性蚀刻工艺中，上述间隔区域内的硅衬底的一部分可被保护而不被暴露。 因此，在间隔区域中不形成金属硅化物，实现上述目的。