公开(公告)号：US20070284605A1

公开(公告)日：2007-12-13

申请号：US11518936

申请日：2006-09-12

申请人： Ying-Tso Chen ,  Teng-Huei Huang

发明人： Ying-Tso Chen ,  Teng-Huei Huang

IPC分类号： H01L33/00

CPC分类号： H01L25/167 ,  H01L33/60 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.

摘要翻译： 公开了一种适用于承载发光二极管管芯和抗静电管芯的铸件。 铸件包括用于相对电极和壁的两个电极。 发光二极管管芯安装在电极之一中，防静电管芯安装在另一个电极上。 壁布置在发光二极管管芯和防静电管芯之间。 此外，壁的高度大于防静电模具的高度以遮蔽防静电模具，从而反射从发光二极管管芯发射的光。 因此，发光二极管管芯的反射率提高，并且由整个发光二极管产生的强度也得到改善。

公开(公告)号：US06548406B2

公开(公告)日：2003-04-15

申请号：US09930998

申请日：2001-08-17

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L21302

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L29/66833

摘要： A method for forming an integrated circuit having metal-oxide nitride-oxide semiconductor (MONOS) memories and mixed-signal circuits is disclosed. The invention integrates non-volatile memory devices such as MONOS devices and logic devices such as MOS devices as well as PIP capacitors into SOC devices with reduced process steps.

摘要翻译： 公开了一种形成具有金属氧化物氮化物半导体（MONOS）存储器和混合信号电路的集成电路的方法。 本发明将诸如MONOS器件的非易失性存储器件和诸如MOS器件的逻辑器件以及PIP电容器集成到具有减少的工艺步骤的SOC器件中。

公开(公告)号：US06448126B1

公开(公告)日：2002-09-10

申请号：US09682217

申请日：2001-08-07

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823412

摘要： A method of forming an embedded memory integrating nitride read only memory starts by forming an ONO layer and a protective cap layer on a surface of a semiconductor substrate defined with a memory area and a periphery area. The periphery area has a first, a second and a third device area. An etching and a first ion implantation process form each bit line in the memory area. A spacer is then formed at either side of the protective cap layer and the ONO layer in the memory area, and the protective cap layer and the ONO layer are removed in the first device area. The threshold voltage for the first device area is adjusted and a first thermal oxidation process forms a buried drain oxide layer atop each bit line and a first gate oxide layer on the surface of the first device area, respectively. The protective cap layer and the ONO layer are removed from the second device area and the third device area, and a second gate oxide layer is formed in the second device area and the third device area. Finally, the protective cap layer in the memory area and the second gate oxide layer in the third device area are removed, and a third gate oxide layer is formed in the third device area.

摘要翻译： 集成氮化物只读存储器的嵌入式存储器的形成方法首先通过在由存储区域和周边区域限定的半导体衬底的表面上形成ONO层和保护覆盖层。 周边区域具有第一，第二和第三设备区域。 蚀刻和第一离子注入工艺在存储区域中形成每个位线。 然后在保护盖层和存储区域中的ONO层的任一侧形成间隔物，并且在第一装置区域中去除保护盖层和ONO层。 调整第一器件区域的阈值电压，第一热氧化工艺分别在第一器件区域的表面上的每个位线和第一栅极氧化物层的顶部形成掩埋的漏极氧化物层。 从第二设备区域和第三设备区域去除保护盖层和ONO层，并且在第二设备区域和第三设备区域中形成第二栅极氧化物层。 最后，去除存储区域中的保护盖层和第三器件区域中的第二栅极氧化物层，并且在第三器件区域中形成第三栅极氧化物层。

公开(公告)号：US20100133576A1

公开(公告)日：2010-06-03

申请号：US12702574

申请日：2010-02-09

申请人： Ying-Tso Chen ,  Teng-Huei Huang

发明人： Ying-Tso Chen ,  Teng-Huei Huang

IPC分类号： H01L33/00

CPC分类号： H01L25/167 ,  H01L33/60 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.

摘要翻译： 公开了一种适用于承载发光二极管管芯和抗静电管芯的铸件。 铸件包括用于相对电极和壁的两个电极。 发光二极管管芯安装在电极之一中，防静电管芯安装在另一个电极上。 壁布置在发光二极管管芯和防静电管芯之间。 此外，壁的高度大于防静电模具的高度以遮蔽防静电模具，从而反射从发光二极管管芯发射的光。 因此，发光二极管管芯的反射率提高，并且由整个发光二极管产生的强度也得到改善。

公开(公告)号：US07608504B2

公开(公告)日：2009-10-27

申请号：US11468311

申请日：2006-08-30

申请人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

发明人： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

IPC分类号： H01L21/00

CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11568

摘要： A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

摘要翻译： 提供记忆。 存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。 位线设置在基板中。 字线设置在基板上。 字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。

公开(公告)号：US20070269943A1

公开(公告)日：2007-11-22

申请号：US11435458

申请日：2006-05-16

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L21/8234

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 提供了一种制造非易失性存储器的方法。 首先，在基板上形成两个开口。 在两个开口之间的基板上形成包括第一电介质层，电荷存储层，第二电介质层和第一导电层的堆叠栅极结构。 衬套形成在丝束开口的侧壁的底部和一部分上，其中衬垫的顶表面低于衬底的顶表面。 第二导电层形成在两个开口的底部的衬垫上，其中第二导电层的顶表面与衬垫的顶表面共面。 第三导电层形成在第二导电层和衬垫上，其中第三导电层的顶表面与衬底的顶表面平行，并且低于第一介电层的顶表面。

公开(公告)号：US08674410B2

公开(公告)日：2014-03-18

申请号：US13413951

申请日：2012-03-07

申请人： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

发明人： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC分类号： H01L27/118 ,  H01L29/78 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

摘要： A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

摘要翻译： 以下公开了金属硅化物的制造方法。 证明具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。

公开(公告)号：US20130234210A1

公开(公告)日：2013-09-12

申请号：US13413951

申请日：2012-03-07

申请人： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

发明人： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC分类号： H01L27/118 ,  H01L21/82

CPC分类号： H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

摘要： A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is proviced. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

摘要翻译： 以下公开了金属硅化物的制造方法。 证明具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。

公开(公告)号：US08084779B2

公开(公告)日：2011-12-27

申请号：US12702574

申请日：2010-02-09

申请人： Ying-Tso Chen ,  Teng-Huei Huang

发明人： Ying-Tso Chen ,  Teng-Huei Huang

IPC分类号： H01L33/00

CPC分类号： H01L25/167 ,  H01L33/60 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： A casting adapted to carry a light emitting diode die and an anti-static die is disclosed. The casting comprises two electrodes for opposite electrodes and a wall. The light emitting diode die is mounted one of electrodes and the anti-static die is mounted on the other electrode. The wall is arranged between the light emitting diode die and the anti-static die. Further, the height of the wall is larger than that of the anti-static die to shade the anti-static die, whereby reflecting the light emitted from the light emitting diode die. Therefore, the reflection ratio of the light emitting diode die is improved, and the intensity generated by the whole light emitting diode is also improved.

摘要翻译： 公开了一种适用于承载发光二极管管芯和抗静电管芯的铸件。 铸件包括用于相对电极和壁的两个电极。 发光二极管管芯安装在电极之一中，防静电管芯安装在另一个电极上。 壁布置在发光二极管管芯和防静电管芯之间。 此外，壁的高度大于防静电模具的高度以遮蔽防静电模具，从而反射从发光二极管管芯发射的光。 因此，发光二极管管芯的反射率提高，并且由整个发光二极管产生的强度也得到改善。

公开(公告)号：US20090212353A1

公开(公告)日：2009-08-27

申请号：US12434828

申请日：2009-05-04

申请人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

发明人： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

摘要翻译： 非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫， 设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。 层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。 衬垫具有比衬底更低的顶表面。 第二导电层具有与衬垫的顶表面共面的顶表面。 第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。